MSPM0G3505
Full part number: MSPM0G3505SDGS28
Key datasheet specifications and the closest alternatives, ranked by parametric similarity and grounded in the manufacturer datasheet.
This TI datasheet covers the MSPM0G3507, MSPM0G3506, and MSPM0G3505 mixed-signal microcontrollers featuring a CAN-FD interface. Designed for ultra-low-power applications ranging from motor control to smart metering, these 32-bit Arm Cortex-M0+ devices operate at up to 80MHz with supply voltages from 1.62V to 3.6V. Key parameters include two simultaneous sampling 12-bit ADCs running at 4Msps, a 12-bit DAC, four UART interfaces supporting LIN and IrDA, and advanced timers enabling up to 22 PWM channels. The MCU family offers extensive memory options, including up to 128KB flash with ECC and 32KB SRAM, alongside flexible I/O features like 60 GPIOs and multiple low-power modes consuming as little as 1.5µA in standby.
Datasheet parameters
| Parameter | Min | Typ | Max | Conditions |
|---|---|---|---|---|
| quiescent current | — | 40 nA | 80 nA | 3.3V |
| output voltage | 1.38 V | 1.4 V | 1.42 V | BUFCONFIG = 1 |
| output current | — | 4 mA | — | |
| supply voltage range | 1.62 V | — | 3.6 V | |
| input offset voltage | — | 200 µV | 9 mV | Noninverting, unity gain, TA = 25°C, VDD = 3.3V; CHOP = 0x0 |
| gain bandwidth | — | 320 kHz | — | CL = 200pF |
| cmrr | 48 dB | 77 dB | — | Over common mode voltage range; CHOP = 0x0 |
| operating temperature | -40 °C | — | 125 °C | |
| clock frequency | 9.5 MHz | 10 MHz | 25 MHz | |
| reverse voltage | 1.4 V | — | — | VR+sourced from external reference pin (VREF+) |
| input bias current | — | 350 pA | 400 nA | 0.1V<Vin<VDD-0.3V, VDD = 3.3V, CHOP = 0x0; TA = 125°C |
| input capacitance | — | 5 pF | — | |
| propagation delay | — | 32 ns | 50 ns | Output Filter off, Overdrive = 100 mV, High Speed Mode |
| operating frequency | 4 MHz | — | 48 MHz | |
| slew rate | — | 5.5 MV/s | — | DATA = 0x80 → 0xF7F → 0x80, Vref = external reference |
| psrr | 57 dB | 63 dB | — | VDD = 1.7 V to VDDmax, BUFCONFIG = 1 |
| input voltage noise density | — | 43 nV/√Hz | — | Noninverting, unity gain; f = 1 kHz |
| cpu speed | — | 80 MHz | — | |
| program memory size | — | 32 kB | — | |
| ram size | — | 16 kB | — | |
| io count | — | 24 | — | |
| adc resolution | — | 12 bit | — | |
| core size | — | 32 bit | — | |
| rise time | — | — | 3.5 ns | SDIO; VDD ≥ 2.7V, CL = 20pF |
| fall time | — | — | 120 ns | ODIO; VDD ≥ 1.71V, FM+, CL = 20pF-100pF |
| data retention | 60 year | — | — | -40°C <= Tj<= 85°C; years |
| load capacitance | — | 1 pF | — | |
| settling time | — | 800 ns | 1 µs | DATA = 0x1EC->0xFFF->0x1EC, Error < ±2 LSB, Vref = internal reference |
Closest matches to MSPM0G3505
Frequently asked questions
What is the ADC resolution of the MSPM0G3505SDGS28?
The ADC resolution is 12 bit.
What is the maximum clock frequency of the MSPM0G3505SDGS28?
The maximum clock frequency is 10 MHz.
What is the CMRR over the common mode voltage range when CHOP = 0x0?
The CMRR is 77 dB over the common mode voltage range when CHOP = 0x0.
What is the core size of the MSPM0G3505SDGS28?
The core size is 32 bit.
What is the CPU speed of the MSPM0G3505SDGS28?
The CPU speed is 80 MHz.
What is the data retention period for the MSPM0G3505SDGS28 when the junction temperature is between -40°C and 85°C?
The data retention is 60 years.
What is the fall time for ODIO when VDD ≥ 1.71V, FM+, and CL = 20pF-100pF?
The fall time is 120 ns.
What is the gain bandwidth of the MSPM0G3505SDGS28 when CL = 200pF?
The gain bandwidth is 320 kHz when CL = 200pF.