The most common mistake with the ROHM RUM001L02T2CL is taking its headline spec literally. The part is marketed as a "1.2 V drive" MOSFET, so engineers wire a 1.2 V rail to the gate, expect the datasheet's best on-resistance, and then wonder why their load switch is dropping volts and running hot. The 1.2 V figure is a minimum capability, not a recommendation. At 1.2 V gate drive the on-resistance is 18 Ω max; at 4.5 V it's 3.5 Ω max — a more than 5× difference on the same silicon. If you internalize one thing from this post: drive this part at whatever higher rail you have, ideally 2.5–4.5 V, and treat 1.2 V as the emergency floor.
What the RUM001L02T2CL actually is
The RUM001L02T2CL is an N-channel small-signal MOSFET in ROHM's ultra-small VMT3 (often called SOT-723 / SC-105AA) package, rated 20 V drain-source, ±100 mA continuous drain current (±400 mA pulsed), 150 mW power dissipation, with on-resistance of 3.5 Ω max at VGS = 4.5 V. Its datasheet classifies it for "switching" and explicitly ties its low-voltage drive capability to portable, battery-powered equipment — the intended job is on/off switching of small loads (peripherals, LEDs, sub-circuit rails) directly from logic-level or simple drive circuits. It is a low-side switch by construction: source to ground, load on the drain, gate driven by your control signal. It is not a power MOSFET — 100 mA and 150 mW cap it firmly to small-signal work — and it is not a high-side pass element. Switching is fast for its size (td(on) 5 ns, tr 4 ns, td(off) 20 ns, tf 38 ns typ at the datasheet's test conditions), with tiny capacitances (Ciss 7.1 pF, Coss 3.3 pF, Crss 1.7 pF), so it also handles moderate-frequency PWM without meaningful switching loss.
Wiring it up (How do I integrate the RUM001L02T2CL into a design?)
The basic topology is a low-side switch: source grounded, drain to your load's low side, load's high side to your rail (up to 20 V), gate to your control signal. The integration decisions that actually matter:
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Gate drive voltage. This dominates everything. RDS(on) is 3.5 Ω max at 4.5 V, 4.2 Ω max at 2.5 V, 5.3 Ω max at 1.8 V, 9.0 Ω max at 1.5 V, and 18 Ω max at 1.2 V (all at the datasheet's specified test currents). If any rail from 2.5 V to 4.5 V exists in your system, use it for the gate. The on-resistance curve keeps improving past 2.5 V too — typ RDS(on) is ~3.8 Ω at 2 V, ~2.4 Ω at 4 V, ~2.0 Ω at 10 V, with no hard knee — so there's no reason to stop low if you have headroom, as long as you stay within the ±8 V gate abs-max.
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Threshold margin. VGS(th) spans 0.3–1.0 V (specified at VDS = 10 V, ID = 100 µA). The worst-case part turns on right at 1.0 V, which is exactly why 1.2 V drive yields such poor on-resistance — the gate barely clears the threshold. At 1.8–3.3 V logic you're comfortably above threshold max; at 1.2 V you're not.
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Gate pulldown. Keep a source-to-gate pulldown so the off-state gate sits at 0 V, well below the 1.0 V threshold max. With Ciss at 7.1 pF, even a 1 MΩ pulldown gives only a ~7 µs time constant, and the leakage it must overcome is tiny — IGSS is ±10 µA max at ±8 V. Tens to hundreds of kΩ is plenty.
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No external gate clamp needed — usually. The part has a built-in gate–source protection diode, so for normal logic drive (1.8–5 V) you don't need a zener on the gate. Just ensure the driver never exceeds ±8 V, including ringing. Plain CMOS outputs are safe.
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Inductive loads. The internal body (source–drain) diode is rated only 100 mA continuous / 400 mA pulsed at 1.2 V max forward voltage — it is not a freewheel clamp. If you switch a relay or inductor, put a flyback diode across the load (drain side), not across the FET, so the body diode never carries the inductive kick.
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Package reality. It ships as VMT3, 8000 units per 180 mm embossed-tape reel. Budget your stencil and pick-and-place for an ultra-small body, and don't be surprised by the 8k quantity.
What to watch out for (What are the RUM001L02T2CL's limits and traps?)
Beyond the 1.2 V myth, three traps account for most field failures:
Thermal starvation. RthJA is 833 °C/W max — this package has essentially no heat path. At the 150 mW max dissipation and 25 °C ambient you land exactly on the 150 °C junction limit. The power derates linearly above 25 °C at 1.2 mW/°C, reaching 0 mW at 150 °C: 80% at 50 °C, 60% at 75 °C, 40% at 100 °C, 20% at 125 °C. At 100 mA with 4.5 V drive you burn only ~35 mW (~29 °C rise), which is fine — but combining full load current with low gate drive and a warm ambient can blow the entire budget. Compute VDS(on) × ID at your hot condition, not at 25 °C.
Hot-end on-resistance. Typ RDS(on) at 4.5 V swings from 1.9 Ω at −25 °C to 4.0 Ω at 125 °C — roughly 2.1×. Size conduction loss for the 4 Ω hot figure. Meanwhile VGS(th) has a negative temp coefficient (0.6 V typ at 25 °C down to 0.4 V at 125 °C), so turn-on margin actually improves hot — but conduction loss at low drive is worse when cold, compounding the margin problem at the cold end instead.
ESD. The built-in gate–source diode protects the gate against over-voltage to the ±8 V abs-max, but ROHM's own Notice says the product "might cause chip aging and breakdown under the large electrified environment" and explicitly asks you to design an ESD protection circuit. The part is classified as electrostatic-sensitive, requiring grounding, ionization, and humidity control in handling and storage. For exposed nodes — connectors, long harness leads to the gate — add a small series gate resistor plus a low-capacitance clamp. There is no published HBM/CDM rating to lean on; system ESD performance is your design's job, verified against your target standard (e.g. IEC 61000-4-2).
Also note: the datasheet publishes no dv/dt or di/dt limits, and no internal gate resistance or gate charge. The binding constraints are voltage (±8 V gate, 20 V drain) and current (100 mA / 400 mA pulsed at Pw ≤ 10 µs, duty ≤ 1%). At this part's slew rates (~12.5 A/µs turn-on derived from the published times), source inductance induces only tens of millivolts — layout is a thermal and ESD question, not a switching-speed one.
Known limitation: the datasheet contains no numeric reflow profile for the VMT3 package — it requires reflow soldering (flow needs ROHM approval) and defers the temperature profile to a separate ROHM mounting specification. It also warns against highly active halogenous flux. Get the mounting spec before programming your reflow oven.
Testing it (How do I verify the RUM001L02T2CL on the bench?)
The datasheet gives you a reference test circuit and exact conditions — reproduce them to get comparable numbers:
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Replicate the datasheet test clamp. Gate driven through RG = 10 Ω from a pulse generator, drain through RL ≈ 200 Ω to VDD ≈ 10 V, source grounded, at VGS = 4.5 V and ID = 50 mA. Scope the gate and drain transitions with 10%/90% threshold references (the datasheet defines td(on), tr, td(off), tf between those levels, not 50%). Compare against td(on) 5 ns, tr 4 ns, td(off) 20 ns, tf 38 ns typ.
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Gate-drive walk. Sweep the gate from 1.2 V to 4.5 V and confirm VDS(on) tracks the published RDS(on) vs VGS curve. A "high" VDS at 1.2 V drive is correct behavior, not a bad part.
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Thermal ramp. Run at your maximum ambient and load; verify junction rise stays under the derated limit. ROHM's precaution explicitly requires de-rating power with ambient and confirming the junction stays in spec even in sealed enclosures.
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Real transient reproduction. This is a datasheet mandate, not a suggestion: ROHM states that under transient (pulse) loads, "confirmation of performance characteristics after on-board mounting is strongly recommended," and that exceeding the power rating "may negatively affect product performance and reliability." Drive your actual worst-case load on the real board and check VDS stays under 20 V, ID under 100 mA (400 mA pulsed within 10 µs / 1% duty), and gate ringing under ±8 V.
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Margin sweep. ROHM requires external-circuit constants to allow "sufficient margin considering variations" of the part and external components, and says to exercise your own independent verification. Re-test with worst-case gate-resistor and load tolerances, not just nominal.
Troubleshooting (Why is my RUM001L02T2CL circuit misbehaving?)
Work symptoms in this order:
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Load never turns on. Measure the actual gate voltage in-circuit. Below ~1 V the part simply isn't on — VGS(th) max is 1.0 V, and a gate signal near that value is at the ragged edge. A floating gate will also pick up charge and partially turn on an N-channel FET; confirm the pulldown is holding the gate at 0 V when off.
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Turns on but runs hot or the load sees too much voltage. Check RDS(on) against the drive you're actually providing. 9.0 Ω max at 1.5 V and 5.3 Ω max at 1.8 V are expected figures — this is the 1.2 V myth again. Move the gate to a ≥2.5 V rail for 3.5 Ω max. Then compute VDS(on) × ID against the derated 150 mW budget at your ambient.
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Device dead, shorted drain-source. One of the abs-max ratings was almost certainly violated — most often an inductive flyback pushing VDS past 20 V, the body diode carrying more than its 100 mA rating because there's no flyback diode across the load, or gate ringing past +8 V. Scope the drain and gate nodes during the actual switching event.
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Leaking in the off state. Real leakage is tiny: IDSS ≤ 1 µA at VDS = 20 V, IGSS ≤ ±10 µA at ±8 V. Substantial off-state conduction means the gate isn't actually at 0 V — trace the pulldown path — or the device is damaged.
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Slow or odd switching waveforms. The published nanosecond figures assume RG = 10 Ω and 4.5 V drive. A large gate resistor or low drive slows switching regardless of the part; note also that turn-off delay and fall time vary strongly with load current (tf ~200 ns at 10 mA vs ~20 ns at 100 mA), so don't extrapolate the 50 mA table values to your operating point.
The fast triage sequence: measure VGS against the 0.3–1.0 V threshold, measure VDS(on) against the RDS(on) for your drive level, then verify none of the 20 V / 100 mA / ±8 V limits are being exceeded.
Part page: RUM001L02T2CL.