The MSPM0G3507 is TI's top-memory member of the MSPM0G350x family: a Cortex-M0+ mixed-signal MCU running at 32 kHz to 80 MHz from a 1.62 V to 3.6 V supply, with 128 KB of ECC-protected flash, 32 KB of SRAM, and an operating temperature range of −40 °C to 125 °C. It carries CAN 2.0 A/B plus CAN-FD up to 5 Mbit/s, four UARTs, two I2C (Fast-mode Plus, 1 MHz) and two SPI (up to 32 MHz in controller mode on high-speed I/O), two 12-bit ADCs sampling at up to 4 MSPS, comparators, an op-amp, a DAC, an AES/TRNG security block, and a MATH accelerator. TI positions the family for motor control, appliances, UPS/inverters, ePOS, medical, test and measurement, factory automation, industrial transportation, grid infrastructure, and smart metering. Run efficiency is 96 µA/MHz (CoreMark), STANDBY is 1.5 µA with RTC and SRAM retained, and SHUTDOWN is 78 nA with I/O wake — the profile you want for battery-backed, always-on nodes.
Think of this post as a bench bring-up sequence: the checks you run in order, from power rail to first debug connection to design sign-off. Everything below is grounded in the MSPM0G3507 datasheet.
Check 1: Wiring Up the MSPM0G3507
Power and decoupling. The datasheet's application-schematic guidance calls for a 10 µF + 0.1 µF low-ESR ceramic pairing between VDD and VSS, placed as close as possible to the supply pins — loop area at the 0.1 µF end matters more than total capacitance. Use X5R/X7R ceramic, not electrolytic. The 10 µF is the recommended value for most applications; you can adjust it, but larger capacitors slow the power-rail ramp, which matters if you care about fast POR and boot. The VCORE pin needs its own 0.47 µF capacitor placed close to the device with minimal distance to ground, and nothing else may be connected to VCORE — it's a dedicated core-supply bypass, not a filter node.
Reset. NRST must be pulled up to VDD — the datasheet is explicit that without this the device cannot boot. The recommended implementation is a 47 kΩ external pull-up plus a 10 nF capacitor to ground for noise filtering. If an external supervisor or debug probe drives NRST, size its output so it can sink the pull-up current and pull below the reset threshold.
Clocks and ROSC. LFXIN/LFXOUT live on PA3/PA4 (pins 43/44), HFXIN/HFXOUT on PA5/PA6 (pins 45/46), and ROSC on PA2 (pin 42) — commit those pins early because they're clock-specialized. If you enable the SYSOSC frequency calibration loop (FCL), the datasheet requires a 100 kΩ resistor with 0.1% tolerance and TCR of 25 ppm/°C or better between ROSC and VSS — a precision thin-film part; a generic 5% thick-film will degrade FCL accuracy. If you don't use FCL, no resistor is needed and PA2 is available as a normal GPIO.
Pin selection for the 64-LQFP. Table 6-1 lists pins PA28–PA31 and PB0–PB27 only in the 64-LQFP column. That matters: UART2/UART3, SPI1, I2C1, and many extra analog channels are only reachable on the 64-pin package. If you chose the MSPM0G3507 for its four UARTs, you must be on 64 pins — for example UART3_RX is PB13 (pin 1) and UART2 lives on PB15–PB18. Only two pins are 5-V-tolerant, and they are open-drain: PA0 (pin 33) and PA1 (pin 34), the I2C0/UART0 pins. Four pins are high-speed class (PA9, PA12, PA13, PA14, PA19 by structure marking), and critically CAN_TX is PA12 (pin 5) and CAN_RX is PA13 (pin 6) — both high-speed. The analog map is asymmetric: DAC_OUT exists only on PA15 (pin 8), OPA1_OUT on PA16 (pin 9), OPA0_OUT/GPAMP_OUT on PA22 (pin 18), VREF+ on PA23 (pin 24) and VREF− on PA21 (pin 17). If you use an external ADC reference, those two pins are consumed. Wake-capable standard I/O is exactly PA17 (pin 10) and PA18 (pin 11).
Unused pins. Per Table 6-4, set unused PAx/PBx pins to GPIO function (PINCMx.PF = 0x1) and configure each as output-low or as an input using the internal pull-up/pull-down. Floating inputs leak in low-power modes — this is the classic cause of measured sleep current far exceeding the datasheet numbers.
Open-drain pins need external pull-ups. ODIO pins pull low only — there is no high-side PMOS — so I2C or UART on PA0/PA1 requires an external pull-up for a high level; there is no internal 40 kΩ pull on those pins. You can pull them to 5 V directly (VIH max is 5.5 V), which is the whole point of their 5-V tolerance. Standard I/O must stay at or below VDD + 0.3 V — never tie a 5 V pull-up to a standard pin.
Check 2: MSPM0G3507 Limits That Will Bite You
Drive current scales with VDD. For standard-drive I/O (SDIO) with VDD ≥ 2.7 V you can count on VOH = VDD − 0.4 V at 6 mA; at VDD ≥ 1.62 V only 1.5 mA is guaranteed. HDIO pins are 20 mA at VDD ≥ 2.7 V and 10 mA at VDD ≥ 1.71 V with the drive bit set. One honest caveat worth flagging: the feature summary says two 20 mA high-drive I/Os, but the pinout table marks four pins (PA10, PA11, PA28, PA31) as high-drive structure — verify drive current against the I/O electrical table for your specific pin before relying on 20 mA.
Known limitation: the datasheet does not specify an I/O injection-current absolute maximum for the clamps, and ESD sizing of TVS/series protection is general engineering practice on this device, not a datasheet-specified value.
Clamp current is ±2 mA on any pin. Standard I/O inputs are bounded at −0.3 V to VDD + 0.3 V; anything beyond enters the clamp region. Any signal that can swing past the rails — long cables, hot-plug buses — needs a series resistor to keep clamp current under ±2 mA.
Ramp rate and BOR latency. The power-up spec requires |dVDD/dt| ≤ 3 V/s; check your regulator's inrush and ramp against it. BOR propagation delay is 10 µs max in RUN/SLEEP/STOP but 100 µs max in STANDBY — budget up to 100 µs of undetected brownout in standby.
Switching speed and clocks. High-speed I/O with DRV=1 toggles up to 40 MHz at VDD ≥ 2.7 V (24 MHz at ≥ 1.71 V); SDIO reaches 32 MHz at ≥ 2.7 V. SPI hits 32 MHz only in controller mode on HSIO pins at VDD 2.7–3.6 V (24 MHz below that, 16 MHz on non-HSIO pins, 16 MHz in peripheral mode). I2C Fast-mode Plus at 1 MHz requires an input clock of 20–32 MHz in power domain 0.
Analog reference details. ADC input range is 0 V to VDD. The internal VREF is 1.4 V (needs VDD ≥ 1.62 V) or 2.5 V (needs VDD ≥ 2.7 V). If you use the internal reference, VREF+ needs 0.7–1.15 µF decoupling (typ 1 µF), the module must only be enabled with that capacitor connected, and VREF+ must be tied to VREF−/GND while internal reference is in use. VREF+ is a driver output with max 100 µA drive — don't try to power anything from it.
Two quirks with real power and timing costs. The analog-mux VBOOST feature adds 0.8 µA when MCLK/ULPCLK runs from LFCLK but 8.5 µA when it doesn't (SYSOSC at 4 MHz), with a 12 µs startup time — gate it off when not sampling. With FCL enabled, SYSOSC undershoots its target by up to −11% during the post-wake settling time, so don't start precision timing (UART baud, timer capture) immediately after exiting a low-power mode.
Flash endurance. Sectors are 1 kB. The lower 32 kB of flash is rated for 100,000 program/erase cycles; the remaining 96 kB gets 10,000. Put frequently rewritten data (logs, counters) in the lower region with wear-leveling, and put calibration data in ECC-corrected regions.
Check 3: Testing the MSPM0G3507
Verify in this order, before loading any application code:
- Rail check: scope VDD through power-up. Confirm it settles in the 1.62–3.6 V window, never exceeds the 4.1 V absolute maximum, and ramps at no more than 3 V/s.
- Reset check: confirm NRST sits high at rest (47 kΩ pull-up present) and that pulling it low resets the device. A floating NRST is the most common cause of a board that does nothing on power-up.
- Debug connection: connect SWD (SWDIO on PA19, SWCLK on PA20) and keep the debugger's SWD clock at or below 10 MHz — that's the datasheet's hard fSWD limit. If connection is flaky, drop to 1 MHz first.
- Clock check: if FCL/ROSC is populated, measure SYSOSC accuracy after settle; remember the −11% wake undershoot when interpreting immediate-post-wake frequency.
- Sleep current: measure supply current in SHUTDOWN expecting 78 nA (plus your board's leakage) and STANDBY expecting 1.5 µA with RTC/SRAM retention. If you read orders of magnitude more, suspect floating unused pins or the 8.5 µA VBOOST overhead.
- Analog check: with the internal 2.5 V reference enabled, confirm the VREF+ pin decoupling (1 µF typical) and verify a known DC input converts correctly; note ENOB is 10.16 bits with the internal 2.5 V reference versus 11.1 bits with an external reference at full speed.
- Wake timing: verify measured wake latency — 22.7 µs from STANDBY, roughly 250–270 µs from SHUTDOWN — and that GPIO wake works specifically from PA17/PA18 if you're using a standard pin.
Check 4: Troubleshooting the MSPM0G3507
Work through these in sequence — most failures are hardware, not code:
- Device doesn't boot at all: check that NRST is pulled up to VDD; the datasheet states the device cannot boot otherwise. Then scope the VDD ramp against the dVDD/dt requirement — POR/BOR only triggers and releases correctly when the slope is within spec, and a ramp that's too fast or too slow produces exactly this symptom.
- Random resets or intermittent brownouts: don't trust a multimeter's steady-state reading. Use a scope to catch microsecond-scale VDD droops; BOR latency is 10 µs max in RUN modes and up to 100 µs in STANDBY, so a fast transient can momentarily drop the core below spec without an immediate visible reset.
- Unstable operation or noise issues: verify the 10 µF + 0.1 µF low-ESR ceramic decoupling is actually present, actually ceramic, and actually within a few millimeters of the pins — substitutions and long loops both show up as marginal behavior. Confirm the 0.47 µF VCORE capacitor is in place and routed close; a missing or distant VCORE cap destabilizes the core rail.
- Debugger won't connect: reduce SWD clock below 10 MHz (the datasheet limit), then re-check the power and reset items above before blaming the IDE or drivers.
- Sleep current is too high: apply the Table 6-4 rules to every unused pin (GPIO function, output-low or pulled input) and confirm VBOOST is gated off when not sampling — floating inputs and an always-on boosted analog mux are the two most overlooked contributors.
- Garbage on 5 V-adjacent signals: confirm you're on PA0/PA1 (the only 5-V-tolerant pins, VIH max 5.5 V) with external pull-ups fitted, and that no standard pin is seeing more than VDD + 0.3 V. ODIO pins do retain voltage tolerance even when VDD is unpowered, but treat that as failure protection, not a substitute for proper power sequencing.
The full order: VDD waveform and ramp rate → NRST pull-up → 10 µF + 0.1 µF decoupling and VCORE cap → SWD clock ≤ 10 MHz → unused-pin configuration. Each step maps to a specific datasheet requirement, so when something fails you know exactly which spec to re-read.
Part page: MSPM0G3507.