The ES8311 is a low-power mono audio codec from Everest Semiconductor: a 24-bit delta-sigma ADC and DAC with an integrated headphone driver, controlled over I²C and streaming audio over I²S/PCM. Its signal path runs mic-in (MIC1P/MIC1N, with a differential option) through a PGA into a mono ADC with ALC, noise gate, and noise-reduction filtering, then out through a mono DAC with dynamic range compression and pop/click suppression to a differential headphone driver on OUTP/OUTN. Headline performance is 100 dB SNR (typ, A-weighted) on the ADC and 110 dB on the DAC, at roughly 8 mA normal-operation current with essentially zero in power-down. It targets battery-powered voice products, wearables, and host-MCU designs — one chip doing capture and playback, with flexible clocking (256/384·Fs, USB 12/24 MHz, and non-standard clocks like 16/25/26 MHz) so it can run from an MCU or USB host without a dedicated audio crystal. This post walks through the datasheet numbers that actually constrain a design, how to wire the part up, how to verify it, and what to do when it misbehaves.
The numbers engineers misread on the ES8311
Most integration pain with this part traces back to a handful of specs that are easy to skim past. Here they are, with what each one means in practice.
Digital I/O thresholds are referenced to PVDD, not DVDD. The input-high threshold is 0.7·PVDD and input-low is 0.5 V max. This is the single most common misread: if you run PVDD at 3.3 V but drive I²S/I²C from a 1.8 V-logic host, your high level (1.8 V) never reaches the 2.31 V threshold and the part simply doesn't respond. Either tie PVDD to your host's I/O rail or level-shift. The digital input absolute-maximum window is DGND−0.3 V to PVDD+0.3 V, so overdriving PVDD-pinned inputs from a higher rail is also a reliability risk.
Full-scale analog level scales with AVDD. Both the ADC full-scale input and the DAC full-scale output are AVDD/3.3 Vrms — about 1 Vrms at AVDD = 3.3 V. Because the reference is literally the supply, AVDD noise and ripple modulate your signal ceiling and directly degrade SNR. A clean, well-decoupled AVDD LDO isn't optional if you want anywhere near the headline SNR figures.
The ADC input is only 6 kΩ. A high-impedance microphone or preamp output connected directly will be loaded down and read "weak." The reference circuit puts a 2.2 kΩ series resistor and 0.01 µF coupling cap on MIC1P; buffer your source so it can drive 6 kΩ. Keep the input within AGND−0.3 V to AVDD+0.3 V absolute maximum.
The 110 dB SNR figure is a DAC spec. The ADC is 100 dB typ / 95 dB min; the DAC is 110 dB typ / 100 dB min. Quoting 110 dB for the record path is a spec-sheet error waiting to happen. THD+N is −93 dB typ on the ADC and −80 dB typ on the DAC.
All AC specs are characterized at one operating point only. Every SNR/THD/filter figure is quoted at AVDD = DVDD = 3.3 V, Fs = 48 kHz, MCLK/LRCK = 256. Other clock ratios (64/128/384/512·Fs, USB 12/24 MHz) are supported per the clock section, but the headline numbers were never characterized there — treat 256×/48 kHz as the only certified operating point.
The digital filter's passband is not Fs/2. Passband edge is 0.4535·Fs (single speed) or 0.4167·Fs (double speed), with the stopband starting at 0.5465·Fs / 0.5833·Fs. Don't expect flat response near Nyquist, and don't fail a frequency-response test at 20 kHz with Fs = 44.1 kHz — that roll-off is by design.
Wiring the ES8311 into your design
Three supplies, decoupled independently. AVDD (analog, pin 11), DVDD (digital core, pins 4/5), and PVDD (pad/I/O, pin 3) are separate rails. Recommended operating ranges: DVDD and PVDD 1.6–3.6 V, AVDD 1.7–3.6 V — note AVDD's minimum is higher, so a 1.65 V rail is legal on the digital side but out of spec on analog. Mixed rails are a supported configuration: the DC table specifies DVDD = PVDD = 1.8 V with AVDD = 3.3 V, and normal-operation current (8 mA typ) is quoted at exactly that combination. Decouple each rail with a 10 µF + 0.1 µF pair per the typical application circuit.
Reference decoupling nodes. VMID, ADCVREF, and DACVREF are "filtering capacitor connection" pins — the caps are required, not optional. Missing them is a frequent cause of analog-path noise.
I²C pull-ups terminate to PVDD. The reference circuit uses 4.7 kΩ on SDA/SCL (CDATA/CCLK); since the high threshold is 0.7·PVDD, pulling up to any other rail risks violating it. The bus runs up to 400 kbps, MSB first, each byte ACKed by the receiver pulling CDATA low.
CE is the address pin. The 7-bit chip address is the fixed pattern 0011 00x, where x equals the CE pin state — exactly two possible addresses, selected by the CE strap, not by any register. The reference circuit shows no pull-up or pull-down on CE; don't add one unilaterally.
Mic input path. MIC1P (pin 18) and MIC1N (pin 17) are the differential pair; the reference single-ended path is a 2.2 kΩ series resistor plus 0.01 µF coupling cap on MIC1P.
Headphone output. OUTP/OUTN are a differential pair, each AC-coupled with 10 µF in the reference circuit — that 10 µF sets the low-frequency corner into your load. Don't shrink it without checking your bass target.
Clocks and the serial audio port. MCLK ≤ 51.2 MHz at 40–60% duty, LRCK ≤ 200 kHz at 40–60% duty, SCLK ≤ 26 MHz with both pulse widths ≥ 15 ns. The port supports I²S, left-justified, right-justified, and DSP/PCM formats. Edge discipline is asymmetric: DSDIN (DAC input) is sampled on the rising edge of SCLK, ASDOUT (ADC output) is driven on the falling edge — the standard I²S convention maps directly, but double-check if you use unusual clock polarities.
Known limitation: The datasheet does not specify a minimum stable headphone load impedance, output power, thermal resistance (θJA), ESD ratings, or a recommended land pattern. The reference circuit also shows no TVS/ESD components — if your analog inputs are exposed (line-in jacks, automotive aux), add your own clamping sized to keep every pin inside the absolute-max windows. The register map (volume ranges, step sizes, reset sequencing) is likewise not covered here; don't assume values for any of it.
Verifying the ES8311 on your board
A staged bring-up catches most problems before they look like audio problems:
- Power and static checks. Measure all three rails at the pins: AVDD ≥ 1.7 V, DVDD and PVDD ≥ 1.6 V. Measure supply current — expect ≈8 mA typ in normal operation and ≈0 µA in power-down at the 1.8/1.8/3.3 V combination. A much larger draw means a short, wrong configuration, or a pin conflict.
- Control interface. Apply MCLK within 40–60% duty at ≤ 51.2 MHz. Confirm the device ACKs at address 0011 00CE. Write a scratch register and read it back — using the two-phase read described below, not a generic repeated-start read.
- Digital audio path. Scope SCLK (≤ 26 MHz, both pulse widths ≥ 15 ns) and LRCK (≤ 200 kHz, 40–60% duty). With the ES8311 as audio master, SDOUT is valid ≥ 11 ns after the SCLK falling edge. Duty or timing violations here corrupt samples no matter how clean the source is.
- Capture path. Inject a full-scale tone (AVDD/3.3 Vrms ≈ 1 Vrms at 3.3 V) into MIC1P and stream out ASDOUT. Expect SNR ≥ 95 dB min (100 dB typ, A-weighted), THD+N ≈ −93 dB typ (−85 dB max), gain within ±5%. Verify your source holds level into the 6 kΩ input.
- Playback path. Play a digital sine via DSDIN and measure the differential OUTP/OUTN pair: full-scale AVDD/3.3 Vrms, SNR ≥ 100 dB min (110 dB typ), THD+N ≈ −80 dB typ (−75 dB max).
- Power-down. Enter power-down and confirm current collapses to ≈0 µA, then resume and confirm audio returns — this validates both the power-management path and pop/click suppression.
- Temperature. Soak at −40 °C to +105 °C and re-run the power, capture, and playback checks at the corners.
Troubleshooting the ES8311
Device not responding on I²C. First check the address: it's the fixed pattern 0011 00CE, so a bus scan should hit 0x30 or 0x31 depending on the CE pin. If it doesn't, check the CE strap, not the part. Second, check bus levels: a 1.8 V host on a 3.3 V PVDD can't meet the 0.7·PVDD threshold — verify your pull-up rail matches PVDD.
Writes work, reads return garbage. This is the ES8311's documented trap: register reads require two phases. First send an access with R/W = 0 to present the register address, then a fresh start with R/W = 1 to read the data. A one-shot repeated-start read returns wrong data. Verify your MCU driver explicitly performs the two-step sequence.
No or distorted playback. Check the clock ceilings with a scope: SCLK ≤ 26 MHz with ≥ 15 ns pulse widths, LRCK ≤ 200 kHz, MCLK ≤ 51.2 MHz, all at 40–60% duty. Marginal SCLK pulse width is the classic cause of corrupted samples. Also verify AVDD is at the expected rail, not merely "present" — full-scale output is AVDD/3.3 Vrms, so a sagging AVDD reads as weak output.
Weak or clipping mic capture. The 6 kΩ input impedance loads high-impedance sources down; buffer the source. Signals above AVDD/3.3 Vrms full scale will clip. If SNR measures below the 95 dB minimum, check AVDD cleanliness — the reference scales with that rail.
Noise or THD worse than spec. The part should deliver ADC SNR 100 dB typ / THD+N −93 dB typ and DAC SNR 110 dB typ / THD+N −80 dB typ at the characterized operating point. If you measure worse, suspect the front end — input loading, supply noise, unbalanced OUTP/OUTN drive, or missing VMID/ADCVREF/DACVREF decoupling — before suspecting the codec. Roll-off above 0.4535·Fs (single speed) is normal filter behavior, not a defect.
Part dead or drawing excessive current after power-up. Check each rail against its minimum (1.6 V digital, 1.7 V analog) and every pin against the absolute-max windows: supplies −0.3 to +3.6 V, analog inputs AGND−0.3 V to AVDD+0.3 V, digital inputs DGND−0.3 V to PVDD+0.3 V. Overstress beyond those windows can cause permanent damage.
Flaky I²C or noisy analog after layout changes. Confirm the reference-circuit values actually made it into the build: 10 µF + 0.1 µF on each supply, caps on VMID/ADCVREF/DACVREF, 10 µF on each headphone output, series resistance and coupling on the mic input, and correctly railed I²C pull-ups.
Need stereo I/O or a fuller feature set than this mono ADC+DAC gives you? See the ES8388 bring-up checklist for the full-stereo sibling in the same Everest family.
Part page: ES8311.