The most common wrong assumption about the DRV8837 is that it's a generic, drop-in 1.8 A H-bridge: wire it up like any other motor driver, drive the inputs with whatever your MCU puts out, and let the built-in protections handle the rest. All three parts of that assumption are wrong in ways that will cost you a bring-up cycle. Its logic thresholds are ratiometric to VCC, not fixed TTL levels — so a 3.3 V MCU cannot reliably drive it at higher VCC. Its interface is PWM on IN1/IN2, not the PH/EN scheme of its near-twin the DRV8838, and the timing tables of the two parts overlap just enough to get cross-contaminated. And its overcurrent protection auto-retries rather than latching off, which means it can masquerade as an intermittent mechanical fault. This post walks through what the part actually is, how to integrate it, the traps, a test sequence, and a troubleshooting triage order.
What the DRV8837 actually is
The DRV8837 is a low-voltage brushed-DC motor driver from Texas Instruments: a single integrated H-bridge rated for 1.8 A peak output current, with a motor supply range of VM 0–11 V and a separate logic supply of VCC 1.8–7 V. It drives one DC motor — or, per the datasheet, "other devices like solenoids" — with four bridge states available: forward, reverse, brake, and coast. Control is via a PWM interface on two pins (IN1/IN2), with externally applied PWM rated 0–250 kHz, and the part operates over −40 to +85 °C ambient. Sleep current is low enough for battery products: 120 nA max total (VM pin 30 nA typ / 95 nA max, VCC pin 5 nA typ / 25 nA max at VM = 5 V, VCC = 3 V). The stated target market is cameras, consumer products, toys, and other low-voltage or battery-powered motion control. It comes in a small DSG (WSON) package with RθJA 60.9 °C/W. In short: a compact, protected, two-rail bridge for small inductive loads — not a stepper driver, not a high-voltage driver, and not pin-compatible in behavior with the DRV8838.
Wiring the DRV8837 into your design (How do I integrate the DRV8837?)
Plan two rails — or justify tying them. VM and VCC are independent supplies. Recommended operating is VM 0–11 V, VCC 1.8–7 V. If your system supply sits between 1.8 V and 7 V, you may tie VCC to VM — the datasheet explicitly allows this, and the two supplies can be applied or removed in any order, so there's no sequencing rule to violate. If you keep them separate, remember the logic interface runs off VCC, not VM; motor voltage does not set your logic level.
Decoupling is specified; bulk capacitance is not. Bypass both VM and VCC to GND with 0.1 µF low-ESR ceramic capacitors, placed as close to the respective pins as possible, with a thick trace or ground-plane connection back to the device GND pin. That's the one capacitor value the datasheet hands you. For the VM bulk capacitor, the datasheet deliberately gives no number: it says adequate bulk keeps the motor voltage stable under high transient current, that the right size depends on motor peak current, supply capability, parasitic inductance, acceptable ripple, motor type, and braking method, and that sizing it requires system-level testing. The one hard rule it does state: the bulk cap's voltage rating must exceed the operating VM voltage with margin for regenerative back-EMF when the motor brakes into the supply.
You don't need external pulldowns or series resistors on the logic inputs. Each input pin — IN1, IN2, and nSLEEP — has a ~100 kΩ internal pulldown to ground. Floating inputs therefore fail safe toward the disabled state. The inputs can also be driven with or without the supplies present, with no leakage current path to the supply, so no series protection resistors are required.
External fault protection is largely built in. The part includes per-FET analog overcurrent protection, VCC undervoltage lockout, and overtemperature shutdown. You don't need an external comparator or TVS for basic short-circuit coverage (short to VM, short to GND, or OUT1-to-OUT2 are all detected). Add external protection only for conditions outside the part's envelope, such as VM transients beyond the ratings.
One part-specific wiring option: two independent half-bridges. Beyond the single full-bridge configuration, the DRV8837 supports independent half-bridge control: two inductive loads tied between VM and each output, with the two control signals swapped before feeding IN1/IN2. Each load energizes when its control bit is high and discharges when low. If you run two half-bridges at independent PWM frequencies or duty cycles, the datasheet recommends placing Schottky diodes with forward voltage < 0.6 V across the motors — more on why below.
What the datasheet warns you about (What are the gotchas when using the DRV8837?)
The input thresholds track VCC — this is the trap that bites people. V_IL and V_IH for IN1/IN2/nSLEEP are specified as ratios of VCC, not fixed voltages: V_IL is guaranteed low below 0.25 × VCC, and V_IH is guaranteed high above 0.5 × VCC (typ 0.46 × VCC, with 0.08 × VCC typical hysteresis). Concretely: at VCC = 1.8 V the thresholds are < 0.45 V / > 0.90 V; at 3.3 V, < 0.83 V / > 1.65 V; at 5 V, < 1.25 V / > 2.50 V; at 7 V, < 1.75 V / > 3.50 V. The practical rule: your MCU's output-high voltage must exceed 0.5 × VCC. A 3.3 V MCU comfortably drives the part at VCC = 3.3 V, is marginal at VCC = 5 V, and fails the > 3.5 V threshold at VCC = 7 V. Keep VCC at or below your MCU's logic-high level, or level-shift. Separately, the pins themselves are rated 0–5.5 V for logic levels (−0.5 to 7 V absolute max) regardless of the ratio math — don't drive them from anything referencing a higher VM rail.
The 1.8 A / 1.9 A margin is thin. Recommended peak output current is 0–1.8 A, but overcurrent protection trips at IOUT > 1.9 A (min) — and the trip point is only bounded as 1.9–3.5 A, with no typical value published. A motor whose stall or inrush current sits near 1.8 A will intermittently trip OCP and enter the auto-retry cycle, which can look like a jam, one-direction-only behavior, or random run/stall. Check your motor's worst-case stall current against that band before committing to the part.
OCP auto-retries — it is not a latch. When overcurrent persists past the deglitch time t_DEG (1 µs typ), all FETs disable; operation resumes automatically after t_RETRY (1 ms typ). Both values are typical-only, with no min/max bounds in the datasheet. The consequence: a persistent stall produces a continuous disable/retry cycle, not a latched-off state. Your software cannot treat OCP as a coarse stall detector without accounting for the fact that the bridge keeps coming back on its own.
VCC has UVLO; VM does not. The bridge disables below VCC < 1.7 V and re-enables above 1.8 V — a dipping logic rail silently kills drive. VM has no equivalent lockout: as long as VCC is above 1.8 V the logic stays active even with VM near 0 V, though the load cannot be sufficiently driven at low VM. If your battery can sag under load, the fix is external — a supply supervisor or adequate bulk capacitance on VM — not an expectation that the driver will shut itself down. Also verify no reverse polarity or negative transient on VM: the absolute-max floor is −0.3 V, and the driver won't guard you from a reversed supply.
Thermal budget is yours to compute. Driver power dissipation is dominated by the output FET resistance: combined HS+LS rDS(on) is 280 mΩ typ / 330 mΩ max at 25 °C, 800 mA, with losses scaling as rDS(on) × I_OUT(RMS)². Junction temperature must stay below the 150 °C abs-max / TSD trip, and the DSG package gives RθJA 60.9 °C/W, RθJC(top) 71.4 °C/W, RθJB 32.2 °C/W. At high average current and hot ambient, size your copper accordingly — the recommended-operating table itself flags that power dissipation and thermal limits must be observed.
Decay mode matters under PWM. During PWM operation the part cycles between two braking modes: mode 1, where both high-side FETs tri-state and recirculation flows through the high-side body diode, and mode 2, where the low-side is off, the high-side on, and recirculation flows through the MOSFET itself. Which mode you're in depends on the state of the other half-bridge input. The more time spent in braking mode 1, the lower the motor's average speed, because more power burns in the body diode — hence the Schottky recommendation for independent-PWM half-bridge use. Under simple on/off control (constant high/low), the two modes don't interact and there's no impact on average speed. And if you need genuine coast, drive IN1 = IN2 = 0: both outputs tri-state (Z), which is distinct from the dead-short brake state.
Don't confuse it with the DRV8838. The 8837 uses a PWM interface on IN1/IN2; the 8838 uses PH/EN. In the shared timing table, t1–t6 are the 8838's PHASE/EN parameters; the 8837's verified numbers are t7–t12 and t_wake. Cross-applying the wrong rows is a classic bring-up error.
Verifying the DRV8837 on the bench (How do I test the DRV8837?)
A workable sequence, power-on to fault testing:
- Safe bring-up. Apply VCC within 1.8–7 V and VM within 0–11 V; confirm VM stays under the 12 V abs-max and VCC under 7 V under all load and sag conditions. Hold nSLEEP low so the device starts in sleep.
- Sleep current. With nSLEEP low and no load, measure quiescent draw against VM pin 30 nA typ / 95 nA max, VCC pin 5 nA typ / 25 nA max (VM = 5 V, VCC = 3 V). A reading orders of magnitude higher usually means nSLEEP isn't actually low or an input is floating.
- Wake and control-table check. Raise nSLEEP — the part is active within t_wake ≤ 30 µs. Step IN1/IN2 through all four states and confirm forward, reverse, brake (both outputs driven), and coast (both outputs Hi-Z).
- Scope the timing. Verify output enable t7 ≤ 300 ns, disable t8 ≤ 300 ns, INx-high→OUTx-high t9 ≤ 160 ns, INx-low→OUTx-low t10 ≤ 160 ns, and rise/fall t11/t12 at 30–188 ns. Grossly slow edges point to poor gate drive, excessive output capacitance, or a bad ground return.
- Reference load. With a known motor or resistive load, confirm each bridge state produces the correct polarity and current on OUT1/OUT2, within the 0–1.8 A recommended peak.
- Supply behavior under load. Monitor VM for sag with the motor under real load — this is where you validate your bulk capacitor, since the datasheet explicitly leaves its value to system-level testing.
- Fault injection. Force IOUT above 1.9 A and confirm the bridge disables and recovers after t_RETRY; drop VCC below 1.7 V and confirm disable, re-enable above 1.8 V; heat the junction past the 150 °C TSD trip (controlled heating only) and confirm shutdown and recovery. During each fault, confirm the outputs are truly tri-stated.
- Thermal soak. At maximum average current and worst-case ambient up to 85 °C, measure board temperature and confirm the junction stays clearly below 150 °C using the RθJA / RθJB figures.
Known limitation: the t_DEG (1 µs) and t_RETRY (1 ms) values are published as typical only, with no min/max bounds — if your design depends on fault-recovery timing margins, the datasheet gives you a nominal, not a guaranteed spread.
When the DRV8837 circuit misbehaves (Why is my DRV8837 not working?)
Triage in this order: nSLEEP high → VCC in 1.8–7 V → VM in 0–11 V → inputs in 0–5.5 V → check OCP/TSD recovery → verify motor stall current < ~1.8 A. The two most frequent real causes, after wiring errors, are VCC sag tripping UVLO and motor inrush tripping OCP.
- Motor doesn't move at all. The bridge is Hi-Z in three situations: nSLEEP low, any fault active, or no supply. Confirm nSLEEP is high and both rails are in range — below ~1.8 V on VCC, the part simply won't operate.
- Intermittent operation that recovers on its own. Suspect VCC dipping below the 1.7 V UVLO threshold or the junction cycling through 150 °C thermal shutdown. Both recover automatically (above 1.8 V / below 150 °C), so if the problem self-heals, monitor VCC and case temperature rather than chasing firmware.
- Runs one direction, or drives then stops. Scope the output current at start: an inrush spike above the 1.9 A OCP trip triggers disable plus auto-retry, which mimics a jam or directional fault. Remember the trip point can be anywhere in the 1.9–3.5 A band, so you can't design to an exact threshold — only "≥ 1.9 A guaranteed."
- Weak torque, low current draw. The peak drive current is internally limited. If the motor wants more than the part allows, the output clamps and the motor drives weakly — that's a spec mismatch, not a broken board. Pick a driver rated for the motor's stall current.
- High quiescent current in a battery product. Sleep requires nSLEEP low, and TI recommends driving all inputs low when entering sleep for minimum power. The ~100 kΩ internal pulldowns make floating inputs read low, but actively drive them low for lowest draw.
- Odd behavior after power cycling. Don't look for a sequencing bug — VCC and VM can be applied and removed in any order. Look at OCP, TSD, or UVLO instead.
A useful isolation trick: because every input has an internal ~100 kΩ pulldown and can be driven with or without the supplies present, you can manually tie each input low and confirm the outputs go Hi-Z — cleanly separating "is it the driver or the MCU."
Part page: DRV8837.