The DAC8830 is a single-channel, 16-bit, serial-input, voltage-output DAC from Texas Instruments built on an unbuffered multiplying R-2R ladder. It runs from a 2.7–5.5 V supply drawing a typical 5 µA (25 µW at 5 V), settles to 1/2 LSB in 1.0 µs, and delivers 1 LSB INL on the best grade over −40 to +85 °C. Its output is 0 → VREF in unipolar mode, and its reference input can carry AC (1.3 MHz −3 dB bandwidth), which makes it usable both as a precision DC setpoint and as a multiplying DAC for variable gain or attenuation. Typical homes for it are portable battery-powered equipment, automatic test equipment, industrial process control, data acquisition, and optical networking. Its sibling, the DAC8831, adds Kelvin force/sense connections and a bipolar ±VREF configuration.
Below are the questions engineers actually ask when bringing this part into a design, answered from the datasheet.
What do I need to know before choosing the DAC8830?
Which grade should I order? The accuracy grade is binned at the factory, not trimmed externally. "IC" grade is ±1 LSB INL, "IB" is ±2 LSB, "ID" is ±4 LSB — all with ±1 LSB DNL, and all the same silicon. If you need genuine 16-bit linearity, order the C grade; a D-grade part is the identical die but will not meet a ±1 LSB test.
DAC8830 or DAC8831? The DAC8830 is pure unipolar (0 → VREF) in SO-8. The DAC8831 adds Kelvin force/sense pairs for the reference and analog ground and supports a ±VREF bipolar output with an external buffer; it comes in SO-14 and QFN-14. If you just need a single-ended unipolar setpoint, the DAC8830 needs none of the sense wiring. If you need precise, offset-free force/sense measurement, the 8831's Kelvin lines are the reason to switch.
What does power-up look like? Both parts reset to zero code on power-up. In unipolar mode that's 0 V; in bipolar mode (DAC8831) the output resets to −VREF, not zero. That's your guaranteed start state — design any actuator safety logic around it.
How do I integrate the DAC8830 into a design? (Wiring, reference, and buffer)
What drives VREF? The reference input is not a fixed high-impedance pin. It presents a code-dependent, purely resistive load — 9 kΩ minimum in unipolar mode, 7.5 kΩ in bipolar/DAC8831 mode (minimum resistance at code 8555h) — plus 75–120 pF of code-dependent capacitance. A resistor divider hung directly on VREF will load and shift full scale as the code sweeps. Drive it from a low-impedance reference source. The valid VREF range is 1.25 V to VDD; references below 1.25 V reduce accuracy, and full-scale output is set directly by the reference.
What decoupling does it need? Bypass both the reference and supply pins with a 10 µF tantalum in parallel with a 0.1 µF ceramic. The datasheet calls this out explicitly for accurate high-resolution performance — at 16 bits, missing bypassing shows up as noise and error, not a hard failure.
Why is there no output amplifier on-chip, and what do I add? The output is a bare multiplying R-2R node, left unbuffered deliberately to cut power consumption (typ 15 µW at 3 V) and eliminate buffer-added error. That means you must provide an external buffer meeting three datasheet requirements: rail-to-rail input and output, at least 1 MHz −3 dB bandwidth (so it doesn't dominate settling), and the highest practical input impedance. The ladder's output impedance is 6.25 kΩ typ and is constant and code-independent, so buffer bias current flowing through it produces a code-proportional gain error: at VREF = 2.5 V, roughly every ~6 nA of input-bias current costs about 1 LSB of gain error. A bipolar-input op amp in the nanoamp-Ib range would erode your entire linearity budget on that term alone — pick a JFET- or CMOS-input amplifier.
How do I do bipolar output? For ±VREF output (the DAC8831 configuration), use a precision amplifier on a dual power supply. On a single supply, the output buffer typically can't swing to AGND, which degrades specified performance unless you avoid codes near zero.
What about grounding? AGND, AGNDF, and AGNDS are separate pins. If you're not using the DAC8831's Kelvin force/sense lines, tie them together close to the package to minimize lead-to-die voltage drop. On the QFN package, the exposed thermal pad must be connected to analog ground — treat it as a required electrical connection, not optional copper. Keep AGND within −0.3 to +0.3 V of DGND (absolute maximum), and don't let DVDD or any digital pin exceed VDD + 0.3 V.
How does the SPI interface work? It's a standard 3-wire SPI/QSPI/Microwire slave up to 50 Mbit/s. Data is latched on the rising edge of SCLK, MSB first, with CS held low for the full 16 clocks; the low-to-high CS edge commits the word. If CS is not held low across all 16 clocks, data is corrupted — reload a fresh 16-bit word. When CS is high, SCLK and SDI are ignored entirely. A useful part-specific trait: the digital inputs are Schmitt-trigger inputs designed for direct optocoupler interface (0.4 V typ hysteresis), so slow or noisy edges — including straight from an optocoupler in isolated designs — are registered correctly without re-shaping logic. Input current is ±1 µA max, so no pull resistors are required for clean logic.
What are the SPI timing limits? The timing tables are identical at VDD = 3 V and 5 V — this part's interface does not slow down at 3 V. SCLK minimum period is 20 ns (50 MHz max), minimum high/low time 10 ns, CS lead/lag 10 ns, data setup 10 ns, data hold 0 ns (data may change exactly at the rising edge), CS high time between frames 30 ns, and 10 µs from VDD valid to the first CS low after power-up. The LDAC timing rows apply only to the DAC8831, which has an LDAC pin; the DAC8830 has none.
What should I watch out for with the DAC8830?
Absolute-maximum limits to design against:
- VDD to AGND must stay within −0.3 to +7 V. The operating range is 2.7–5.5 V, so never let the rail transient above +7 V or below −0.3 V.
- Digital inputs and VOUT to AGND must stay within −0.3 to VDD + 0.3 V. This is the limit to check for overshoot/undershoot on SPI lines and the output node.
- AGND/AGNDF/AGNDS to DGND must stay within −0.3 to +0.3 V. A split ground plane that drifts apart is a direct violation — keep the grounds tied, and if you use the DAC8831's Kelvin sense lines, the AGNDS/AGNDF potential must stay inside this window.
Spec conditions that may not match your circuit: the electrical characteristics are guaranteed at VDD = 3 V or 5 V with VREF = +2.5 V. If your reference isn't 2.5 V, the published linearity numbers shift — INL degrades below ~2.5 V (typ −0.25 LSB at 2.7 V supply; −0.15 with a low reference). Check the datasheet's curves for your actual VREF rather than assuming the headline specs hold.
Drift and glitch numbers worth knowing: gain drift is ±0.1 ppm/°C typ and zero-code drift ±0.05 ppm/°C typ — typical values only, with no guaranteed max, so your reference and buffer tempcos will usually dominate full-scale drift. Glitch impulse area is 35 nV·s typ at a major carry transition, digital feedthrough 0.2 nV·s typ, and the ladder's own slew rate is 25 V/µs typ at CL = 10 pF — meaning post-glitch settling is dominated by your external buffer, not the ladder.
How do I test a DAC8830 circuit?
Work through these checks in order; each pass criterion is a datasheet spec.
- Power-on reset. With VREF = +2.5 V unipolar, the output should read ~0 V at power-up (zero code reset) before you program anything. This confirms the latch and output chain are alive.
- Transfer function. Sweep the full 16-bit range and check the ideal law: code FFFFh → VREF × 65535/65536 ≈ VREF, code 8000h → exactly ½VREF, code 0000h → 0 V.
- DNL/monotonicity. Every adjacent-code step must stay within ±1 LSB (DNL is ±1 LSB on all grades). A step that comes out small or negative is a monotonicity or assembly fault.
- INL against your grade. The window is ±1 LSB (C), ±2 LSB (B), or ±4 LSB (D). Failing a D-grade part at ±1 LSB is a test-design error, not a device failure.
- Settling. After a large transition (e.g. 0000h → FFFFh), the output should settle to 1/2 LSB within 1.0 µs. Excess glitch or a slow tail usually indicts the external buffer, since the buffer adds its own time constant on top of the ladder.
- SPI timing. Verify against the timing table — and note the tables are identical at 3 V and 5 V, so don't mix rows. Data latches on the SCLK rising edge with CS low for all 16 clocks.
- Abs-max health screen. Confirm in-circuit that no digital or output node exceeds −0.3 V to VDD + 0.3 V, VDD stays within −0.3 to +7 V, and AGND-to-DGND stays within ±0.3 V — do this before trusting any functional result.
- Assembly checks. Confirm the QFN exposed pad is at analog ground and that the 10 µF + 0.1 µF bypassing is present on reference and supply pins.
- Noise floor (optional). The datasheet quotes 10 nV/√Hz noise. Excess broadband noise beyond that — after accounting for your buffer and reference — points to layout or bypassing, not the DAC.
Use a controlled VREF and a high-impedance measurement path with at least 16-bit accuracy throughout.
Why is my DAC8830 circuit misbehaving? (Troubleshooting)
First write after power-up looks wrong. The DAC latch resets to zero code, but the serial shift register is not cleared — its contents are undefined. Loading fewer than 16 bits leaves residual bits in the frame; pad short words with zeros in the LSBs. This is the most common "first write looks garbage" cause.
Output doesn't match what I sent. Check CS/SCLK framing: exactly 16 SCLKs per word, CS low for all 16, CS going high right after the 16th clock to commit. If CS wasn't held low across all 16 clocks, the data is corrupted — rewrite a fresh 16-bit word.
Not communicating at all. Make sure you're sending a full 16-bit frame every time; partial frames leave leftover bits from the previous word.
Output is off scale or drifts with code. Your reference source is too weak. The code-dependent 7.5–9 kΩ input resistance will pull a high-impedance source (like a resistor divider) as the code changes. Add a proper low-impedance reference buffer.
Analog noise is too high. Check the bypassing on reference and supply pins (10 µF tantalum + 0.1 µF ceramic). Missing bypassing degrades 16-bit accuracy as noise, not as a hard failure.
Slow or noisy SPI lines fail. This part is unusually tolerant — the Schmitt-trigger inputs (0.4 V typ hysteresis) are built for direct optocoupler drive. If edges that slow still fail, look at logic levels or edge quality upstream, not at the DAC.
Can't hit the settling or accuracy spec. Remember the output is unbuffered — without an external rail-to-rail, ≥1 MHz, high-input-impedance buffer you won't see datasheet accuracy or settling at all.
Before blaming the part. Verify no node exceeds −0.3 V to VDD + 0.3 V, VDD is within −0.3 to +7 V, and AGND–DGND is within ±0.3 V. A violation of any of these is a design fault, not a device defect.
Part page: DAC8830.