CS1238: A Practical Integration Guide for Chipsea's 24-bit Σ-Δ ADC

The CS1238 from Chipsea is a 24-bit sigma-delta ADC with two differential input channels and an internal temperature sensor, built around a second-order Σ-Δ modulator and a PGA with gains of 1, 2, 64, and 128. Output rates run from 10 Hz to 1.28 kHz, with p-p noise of 150 nV at PGA = 128 and 10 Hz and ENOB of 20.7 bits at 5 V (20.2 bits at 3.3 V). It talks to a host over just two wires — SCLK and a bidirectional DRDY/DOUT pin — needs no external crystal thanks to an internal RC oscillator, and has a built-in power-down mode drawing 0.1 µA. Its stated applications are industrial process control, electronic scales, liquid/gas analysis, blood analyzers, smart transmitters, and portable devices: in short, the classic slow, high-resolution bridge-and-sensor measurement jobs where a load cell or precision transducer feeds a high-gain differential front end.

If you're about to commit this part to a design, work through the checks below in order — before layout, before first power-up, and before you trust a single conversion.

Pre-Flight Check 1: Wiring the CS1238 Into Your Design

The interface is minimal by design: VDD, ground, SCLK, and DRDY/DOUT. No chip-select, no MISO/MOSI pair, no crystal. That simplicity hides most of the integration work in two places: the two-wire protocol and the power/reference plumbing.

The two-wire interface. DRDY/DOUT is one bidirectional pin doing four jobs: conversion-ready flag, 24-bit data output, register-status indicator, and register data I/O. When a conversion completes, the pin pulls low; the first SCLK rising edge clocks out the MSB, and 24 SCLKs shift out the full 24-bit two's-complement word, MSB-first. Because there's no CS pin to gate the bus, your MCU must actively flip the pin between driven and high-impedance at the exact clock edges defined in the frame — or your bus will fight the part.

Register access extends the same frame. After the 24 data clocks, drive 46 SCLKs total: clocks 25–26 report status bits, clock 27 raises DRDY/DOUT, clocks 28–29 switch pin direction, clocks 30–36 carry the command byte, clocks 38–45 move the 8-bit Config data MSB-first, and clock 46 returns the pin to output. Writing config uses command byte 0x65; reading it back uses 0x56 — those are the only two commands the part has.

Power and reference. The datasheet characterizes the part in two supply windows only: VDD = 4.5–5.5 V (typ 5 V) and VDD = 3.0–3.6 V (typ 3.3 V). Absolute maximum is −0.3 to 6 V, so a 5 V rail is fine as long as it doesn't ring past 6 V on hot-plug. REFOUT outputs VDD — it's the intended excitation for a ratiometric bridge, which is exactly why VDD filtering matters so much here: any ripple on the supply lands directly in your reference and your measurement. The LSB weight follows (0.5·V_REF / Gain) / (2²³−1), with full-scale codes 7FFFFFH and 800000H for positive and negative. Use the 5 V rail for the analog side if you can — the ENOB difference (20.7 vs 20.2 bits) is real.

Decoupling caps, TVS diodes, and input RC filter values are engineering practice, not datasheet specs — the datasheet prescribes none of them. For a 24-bit Σ-Δ part, treat low-noise VDD decoupling as mandatory, and protect any analog input that leaves the board; the datasheet publishes no ESD or latch-up ratings, so don't count on internal protection structures.

Pre-Flight Check 2: CS1238 Configuration and Behavioral Gotchas

Several behaviors on this part are inverted or narrower than a typical SPI ADC. Catch them at design time, not on the bench.

• Idle SCLK low, not high. Holding SCLK high for ≥100 µs drops the CS1238 into PowerDown (<0.1 µA); pulling it low for ≥10 µs resumes normal operation, and all configuration is retained across the sleep. A controller that floats SCLK high between transactions will silently power the ADC down. This is the intended battery duty-cycling mechanism — but only if you meant it.
• The Config register is one byte — write the whole thing. Reference switch, output rate, PGA, and channel all pack into a single Config byte. Bit [7] is reserved and must always be written 0. On power-up the register defaults to PGA = 128, 10 Hz, channel A, internal reference output enabled. If your first readings look saturated, ask whether you actually wanted 128× gain.
• External reference requires setting REFO_OFF. The default config has the internal REF output on, so an externally driven reference won't take effect until you clear it in software.
• Match gain to the signal. Full-scale differential input is ±0.5·V_REF/PGA, and the common-mode range shrinks at high gain: PGA = 1/2 allows AGND−0.1 to AVDD+0.1 V, but PGA = 64/128 allows only AGND+0.75 to AVDD−0.75 V. At PGA = 128 you lose 750 mV of headroom per side. Verify your sensor's bias point fits the window for the gain you choose. Also note differential input impedance drops from 210 MΩ at PGA = 1/2 to 29 MΩ at PGA = 64/128 — a high-impedance source can be loaded measurably at high gain.
• Pick your rate for noise, not for speed. SPEED_SEL offers 10/40/640/1280 Hz. For bridge measurements the 10–40 Hz settings trade speed for noise — that's what the Σ-Δ architecture is built around.
• Two channels, but not simultaneously. One ADC is muxed across AINP1/AINN1, AINP2/AINN2, the internal temperature sensor (CH_SEL = 10, which forces gain 1), and an internal-short channel (CH_SEL = 11). Sequential sampling only.
• SCLK edges must be fast. Data is only guaranteed with SCLK rise/fall times under 50 ns, high/low pulse widths of at least 455 ns, and a maximum clock of 1.1 MHz. A series resistor plus line capacitance that RC-slopes the clock is a real, documented failure mode — it causes both read errors and unintended power-down entries.
• The oscillator drifts with temperature. The internal 5.2 MHz RC oscillator has 250 ppm/°C drift, which propagates into your actual output rate. If sample-rate accuracy across temperature matters, plan for rate calibration; and note the datasheet publishes no 50/60 Hz line-rejection figures, so don't count on the digital filter for mains rejection — filter in the analog domain or in software if line pickup is a concern.

Pre-Flight Check 3: CS1238 Bring-Up and Verification

Test in stages, from rails to resolution. Each pass criterion below comes straight from the datasheet.

1. Supply sanity. Confirm VDD sits inside 4.5–5.5 V or 3.0–3.6 V — not between the windows. Measure active current: expect roughly 1.57 mA (PGA = 1/2) or 2.34 mA (PGA = 64/128) at 5 V, or 1.26 mA / 2.11 mA at 3.3 V. Substantially higher current means you're probably not in normal mode.
2. Power-down entry/exit. Hold SCLK high ≥100 µs and watch supply current collapse to ~0.1 µA; pull low ≥10 µs and confirm full recovery. This is a fast, unambiguous "the chip is alive" test that also exercises the sleep convention.
3. Register readback loop. Write a known pattern to Config with command 0x65, read it back with 0x56, and require a bit-for-bit match. This one test exercises the full 46-clock frame and catches wiring, level-shifting, and MCU-direction-control bugs in a single step.
4. Offset and noise. Short the inputs; offset error should be within ±1.4 µV (drift 20 nV/°C). At PGA = 128 and 10 Hz with a 5 V reference, one LSB is about 2.33 nV, so the 150 nV p-p noise spec works out to roughly 64 codes p-p — measure the code spread and compare.
5. Accuracy over the range. Verify INL against ±15 ppm, gain error against ±0.5% (8 ppm/°C drift), and test ENOB at both rails — 20.7 bits at 5 V, 20.2 bits at 3.3 V. On the temperature channel, compare against a known ambient; the sensor is specified at ±3 °C and requires single-point field calibration: measure the code Ya at a known temperature A, then compute any later point as T_B = Yb · (273.15 + A) / Ya − 273.15. There is no factory-fixed mV/°C slope — the calibration anchor is the slope, not the offset.

Pre-Flight Check 4: Troubleshooting the CS1238

When readings look wrong, map the symptom to the cause:

• Saturated or clipped first readings. The power-up default is PGA = 128. A sensor signal that's fine at gain 1 overflows at 128 — and remember the common-mode window is tighter at high gain. Check the Config byte you actually wrote; writing only the field you care about and leaving the rest stale is a classic bug with a packed single-byte register.
• The chip goes to sleep mid-operation or won't respond. SCLK idling high for over 100 µs is PowerDown. Check what your controller does with SCLK between transactions, and check clock edge quality — slow, RC-sloped SCLK edges are a documented cause of both read errors and spurious state failures.
• Stale data / DRDY never falls. After a read, DRDY/DOUT is held high for 300 ms at 10 Hz, 75 ms at 40 Hz, 6.25 ms at 640 Hz, and 3.125 ms at 1280 Hz before the next conversion. Polling faster than the output period just sits on a high pin.
• Readings drift after a channel or gain change. Settle times matter: after power-up, power-down recovery, or a channel switch, the analog needs 2 ms to settle; after a PGA or rate change, 0.8 µs. And the digital filter needs a fixed count of conversions, not a fixed time — 3 cycles at 10/40 Hz, 4 cycles at 640/1280 Hz. At 10 Hz that's 300 ms of settling; discarding the first few conversions after any switch is standard practice here.
• Noise far worse than 150 nV p-p. Suspect supply and reference noise before the part — REFOUT equals VDD, so rail ripple goes straight into the measurement path. Check layout, decoupling, and whether VDD is clean at the pin, not just at the regulator.
• Config reads back wrong. Verify the 46-clock frame timing and, above all, that your firmware tri-states DRDY/DOUT at the correct clock edges — direction control on that single bidirectional pin is the most common source of register-corruption bugs on this interface.

Known limitation: Exact AC/DC electrical characteristics tables and some fine-grained SPI timing rows were not fully retrievable from the source document for this writeup — verify your SCLK edge margins directly against the timing tables in the official datasheet before declaring an interface test complete.

Work these checks in order and the CS1238 is a straightforward, low-component-count path to 20+ effective bits. Skip the timing and config-default checks, and it will happily sleep, saturate, or hand you stale data instead.

Only need one channel? The CS1237 guide covers the single-channel sibling — same gain and configuration traps, minus the second channel.

Part page: CS1238.