CS1237 Integration Guide: Gain, Input Range, and the Settings That Interact

The ChipSea CS1237 is a 24-bit sigma-delta ADC with an integrated low-noise PGA, built for reading microvolt-level differential signals from bridge sensors — load cells, pressure transducers, and similar front ends in industrial process control, electronic scales, chemical analysis, blood glucose meters, smart transmitters, and portable battery devices. In an SOP-8 package, it packs a single differential input (AINP–AINN) with selectable gain of 1/2/64/128, output rates of 10 Hz / 40 Hz / 640 Hz / 1.28 kHz, an internal or external reference, an internal temperature sensor, and a 2-wire SPI-compatible host interface (SCLK + DRDY/DOUT, up to 1.1 MHz). At PGA=128 and 10 Hz it delivers 20-bit ENOB at 5 V (19.5-bit at 3.3 V) with 180 nV P-P noise, while drawing only ~1.3–2.3 mA in normal operation and under 0.1 µA in power-down. If you're bringing one up on a new board, this post walks through the sequence in order: what the part is, how to wire it, which limits to respect, how to verify it on the bench, and what to do when it misbehaves.

What the CS1237 is for (and when to pick it)

ChipSea's own application list for the CS1237 names industrial process control, electronic scales, liquid/gas chemical analysis, blood glucose meters, smart transmitters, and portable devices. The specs back that up: the PGA is explicitly designed to connect to bridge sensors with differential output, the 24-bit two's-complement output and slow rate options suit high-resolution electrochemical measurements, and the sub-µA power-down makes duty-cycled battery operation practical.

One structural point to internalize early: there is exactly one ADC with one differential input. The temperature sensor is a muxed input path selected via ch_sel[1:0], not a second converter — you can't sample your bridge and die temperature simultaneously. If you interleave them, you'll be rewriting the config register between reads (more on the settling cost of that below).

Check 1: Wiring the CS1237 into your design

Analog input conditioning. The input already carries internal filtering: an EMI filter of R=450 Ω + C=18 pF giving roughly 20 MHz of high-frequency rejection in front of the PGA, and a low-pass/anti-aliasing filter at the PGA output formed by an internal 45 pF capacitor at the CAP port together with the internal 2 kΩ RINT. (Separately, the datasheet describes an internal low-pass filter of RINT=2 kΩ with CINT=0.1 µF after the low-noise PGA, discussed in the context of settling error at PGA=64/128.) Two consequences:

• The on-chip EMI filter only handles high frequencies. Add your own RC on AINP/AINN for whatever noise band your environment actually has (50/60 Hz pickup, switching regulators, etc.) — don't expect the internal filter to do that job.
• Don't leave the CAP port unaccounted for. It pairs the internal 45 pF with the internal 2 kΩ RINT to set the PGA-output low-pass/anti-aliasing bandwidth. An internal buffer is used at all gains to reduce settling and gain errors from the input impedance and this RC, so you don't need an external buffer.

SCLK idle state — the one wiring choice the datasheet forces. Holding SCLK high for more than 100 µs puts the entire chip into power-down (< 0.1 µA); dropping SCLK low wakes it with all configuration retained. A floating SCLK line that drifts high will silently shut your ADC down mid-session. Bias SCLK low when idle — a pull-down to ground is the standard approach. The guide gives no pull-resistor value, so the resistance itself is engineering practice; the direction (idle-low) is dictated by the spec. DRDY/DOUT is an output and needs no pull unless you're adding margin against line capacitance.

Decoupling. The guide publishes no bypass-capacitor value. Normal-mode draw is modest — 1.57 mA at 5 V / 1.26 mA at 3.3 V for PGA 1/2, rising to 2.34 mA / 2.11 mA for PGA 64/128 — so a small ceramic close to VDD is all the rail needs. Treat the value as practice, not spec.

Reference. The reference can be internal or external, but to use an external one you must first disable the internal reference via the refo_off bit. If you drive REFIN externally, keep it within 1.5 V to VDD+0.1 V.

Digital interface. The host interface is 2-wire SPI: SCLK plus a shared DRDY/DOUT line, up to 1.1 MHz. Use DRDY to know when a conversion is ready rather than polling on a timer — it's the intended handshake and it simplifies your firmware.

Check 2: The CS1237's gain, input range, and the limits that bite

This is where most CS1237 design errors live, so check each item against your schematic before applying power.

Supply. The part has two distinct operating supply ranges, each with its own spec table: VDD = 4.5–5.5 V (typ 5 V) for 5 V operation, and VDD = 3–3.6 V (typ 3.3 V) for 3.3 V operation — note the gap between 3.6 V and 4.5 V is not a supported operating region. The absolute maximum is −0.3 V to 6 V. That 6 V ceiling is only ~0.5 V above the 5.5 V operating max — if your rail can overshoot on hot-plug or transients, verify it can't breach 6 V. Absolute-max supply current is 100 mA transient / 10 mA steady-state; neither is a concern at normal load, but don't let a supply fault sustain more than 10 mA.

Common-mode range changes with gain. This is the classic trap:

In prose: at low gain the input can swing nearly rail-to-rail, but at gain 64 or 128 the valid common-mode window shrinks to 0.75 V inside each rail — a ground-referenced single-ended signal that worked fine at PGA=2 may be out of range at PGA=128. Level-shift or bias the signal to stay inside the window.

Full-scale span. The differential full-scale input is ±0.5·VREF/Gain, mapping to code 7FFFFFh at +full-scale, 000000h at zero, and 800000h at −full-scale (two's-complement). Check your sensor's maximum differential output against this per chosen gain, or the output will saturate silently — the part gives no overflow flag.

Input impedance. Differential input impedance is 190 MΩ at PGA 1/2 but drops to 28 MΩ at PGA 64/128. Keep external series resistance small enough that it doesn't form a meaningful divider into 28 MΩ, or you'll see a gain error at high gain.

Thermal. All electrical parameters are tested at −40…85 °C ambient; junction max is 150 °C, storage −60…150 °C. Verify your enclosure holds ambient ≤85 °C at full load.

What the guide doesn't give you. The user guide publishes no ESD rating, no latch-up/injection-current spec, and no TVS/clamp component values. If your signal can exceed the rails (sensor fault, cable transient), input protection is on you as engineering practice — the internal EMI filter has no stated clamp.

Known limitation: the retrieved guide contains no explicit ESD/immunity or injection-current rating. If your product must pass ESD or latch-up qualification, that number needs additional vendor documentation rather than this user guide.

Check 3: Configuring the CS1237 correctly

Three CS1237-specific behaviors are easy to miss:

• Power-down is a level, not an edge. SCLK high > 100 µs shuts the chip down; SCLK low wakes it, and all configuration is retained through power-down — gain, rate, channel, reference all survive. But a genuine power-up (POR) auto-resets the chip and clears config. So: no reprogramming needed after sleep, full re-init after a power cycle.
• Settling after any gain or rate change. The analog input and digital filter need 3 conversion cycles at 10/40 Hz, or 4 cycles at 640/1280 Hz to settle. After any pga_sel or speed_sel write, discard the first 3–4 DRDY results — they're stale. This also applies when interleaving the temperature channel, since that requires PGA=1 while your bridge measurement probably doesn't.
• Gain changes the power budget. At PGA=1 or 2 the 64× low-noise front-end amplifier is shut off to save power — that's why the current differs between gain settings. Size your LDO/battery budget for the gain you actually run.

The temperature channel deserves its own note: select it with ch_sel=2'b10, it only operates at PGA=1, and it requires single-point calibration (measure the code at one known temperature, then derive temperature from that anchor). Accuracy is ±3 °C. Don't trust raw temp codes out of the box.

Check 4: Testing and verifying the CS1237 on the bench

Run these in order:

1. Power-on/POR. Apply VDD; the internal POR auto-resets the part and it should begin converting with no manual reset. DRDY/DOUT should assert after the first conversion period.
2. Rate check. There's no external clock pin — the part runs from an internal 5.2 MHz oscillator (with 250 ppm/°C drift, a real limiter if you need timing accuracy over temperature). Time the DRDY interval: conversion time is 100 ms at 10 Hz, 25 ms at 40 Hz, 1.5625 ms at 640 Hz, 0.78125 ms at 1280 Hz.
3. SPI timing. Scope the bus against: DRDY low to first SCLK rising edge ≥ 0 ns (t4); SCLK pulse width ≥ 455 ns (t5), i.e. max ~1.1 MHz; 455 ns setup from SCLK rise to new data valid (t6); 227.5–455 ns hold of the old bit after SCLK rise (t7). If you're bit-banging above 1.1 MHz, you will fail here.
4. Offset/span validation. Short AINP to AINN — the output should read 000000h. Then apply a small known differential and confirm the code against 1 LSB = 0.5·VREF/Gain / (2²³−1). This is your end-to-end gain check.
5. Common-mode sweep. Sweep the input common-mode across your expected span at your production gain setting and confirm the output stays linear — this catches the high-gain window problem described above.
6. Noise floor. With inputs shorted at PGA=128, 10 Hz, histogram the codes: peak-to-peak spread should be consistent with 180 nV P-P, 20-bit ENOB at 5 V (19.5-bit at 3.3 V), INL < 15 ppm. Remember this spec only holds at that exact gain/rate condition.
7. Calibration residuals. Do a two-point calibration and confirm residuals sit within offset ±1.4 µV (drift 20 nV/°C) and gain error ±0.5% (drift 8 ppm/°C), all spec'd at PGA=128.
8. Power-down test. Hold SCLK high > 100 µs and measure VDD current — it should drop below 0.1 µA. This is a definitive check that the part actually entered power-down. Drop SCLK low and confirm conversion resumes with the prior configuration intact.

Troubleshooting the CS1237

Work through these in order of likelihood:

• Readings suddenly stop / part appears dead. Check the SCLK idle level first. If SCLK has floated high or been left high for > 100 µs, the CS1237 is in power-down drawing < 0.1 µA. Pull SCLK low and it resumes with configuration retained. A scope on SCLK idle state diagnoses this in seconds.
• Output saturated at 7FFFFFh or 800000h. Your differential input has exceeded ±0.5·VREF/Gain for the configured gain — either reduce gain, raise VREF (within 1.5 V…VDD+0.1 V for REFIN), or attenuate/condition the signal.
• Works at low gain, garbage at gain 64/128. The common-mode window tightened to AGND+0.75 V…AVDD−0.75 V. Re-check your sensor's common-mode level against the high-gain window, and check that external series resistance isn't forming a divider into the now-28 MΩ differential input impedance.
• Stale or glitchy values right after a config write. You didn't discard settling samples. Throw away the first 3 conversion cycles at 10/40 Hz or 4 cycles at 640/1280 Hz after any gain, rate, or channel change.
• Garbled SPI data. Verify t5/t6/t7 on a scope. The most common cause is clocking faster than 1.1 MHz or sampling DOUT too soon after the SCLK edge — the part needs 455 ns setup and holds the old bit for only 227.5–455 ns.
• Wrong code scale. Confirm which reference is actually active. If you intended an external reference but never set refo_off, the internal reference is still driving the conversion, and your full-scale math (everything is defined against VREF) is off.
• Temperature reading is nonsense. The temp channel only works at PGA=1 and needs single-point calibration. If you left pga_sel at 128 when muxing to the sensor, the reading is invalid — and even at PGA=1, raw codes mean nothing until you've calibrated against one known temperature.
• Noise worse than 180 nV spec. You're probably not at PGA=128, 10 Hz — that's the only condition where the 180 nV / 20-bit figure applies. Also check that you added your own RC for low-frequency bands; the internal 450 Ω/18 pF filter only covers ~20 MHz.
• Config lost after battery swap / brownout. That's expected: POR clears configuration (unlike power-down, which retains it). Re-initialize after any supply interruption.

One last design-review pass: confirm your VDD rail can't exceed 6 V under any transient, your steady-state supply current stays under 10 mA, and your enclosure keeps ambient within −40…85 °C. Those are the damage and spec-coverage limits, and they're the ones you can't fix in firmware.

If you need two channels instead of one, see the CS1238 bring-up guide — same family, same gain/config gotchas, plus what changes with the second channel.

Part page: CS1237.