The ADS131M02 is a 2-channel, simultaneous-sampling delta-sigma ADC from Texas Instruments with an integrated digital filter, a PGA (gains 1/2/4 up through 128), and an SPI interface with CRC on both the communications and register map. Its headline spec is 102 dB dynamic range at 4 kSPS (OSR 1024, gain 1). Target applications per the datasheet include electricity meters, circuit breakers, protection relays, power quality meters, and battery test/management systems — though TI notes the Applications list isn't part of the formal component specification, so suitability validation is on the designer.
New to the ADS131M02? Here are the questions you'll actually ask during bring-up, answered from the part's own datasheet.
How do I trade off noise, OSR, and power mode?
Noise depends only on OSR and gain — not on power mode — so pick OSR for your bandwidth, then choose the power mode (HR/LP/VLP) purely to trade clock frequency vs. supply current.
How do I wire it up?
Clock: CLKIN takes an LVCMOS clock from your MCU or a local LVCMOS buffer — it's not a crystal input, so no load caps. The clock must be present continuously, glitch-free, and at a frequency legal for your selected power mode.
Control pins:
- SYNC/RESET: if unused, tie to DVDD in hardware. Never leave it floating.
- DRDY: may float if unused — but tie either SYNC/RESET or DRDY to the MCU, or samples can be missed.
- CS: tie low if this is the only device on the SPI bus — but then you must enable and use the data-in/data-out CRC.
CAP pin (mandatory, not optional): the internal 1.8 V LDO output needs external bypass. DVDD > 2.7 V → 220 nF from CAP to DGND. DVDD ≤ 2 V → tie CAP directly to DVDD and decouple with 100 nF to DGND.
Decoupling: 1 µF on AVDD and DVDD each, MLCC, as close to the pins as possible. X7R-grade ceramic for supply decoupling; avoid vias to the caps in noisy systems and use multiple parallel ground vias.
Input filter: keep it simple. Because it's a delta-sigma ADC with an integrated digital filter, a single-order RC per channel provides sufficient antialiasing in the vast majority of applications. Use C0G (NP0) caps on the analog inputs — high-K Y5V is not recommended.
Layout: dedicate an entire PCB layer to a ground plane with no signal traces. If you must split planes, connect them at a single point at the ADC — multiple ties create ground loops. Route digital traces away from all analog inputs.
Sequencing: supplies can come up in any order, but analog/digital inputs must never exceed their respective supply rails — clamp inputs before supplies are up.
What's the biggest gotcha?
The integrated negative charge pump. It lets inputs swing below AGND on a unipolar supply — which means shunt diodes between the inputs and AGND cannot be used for negative overvoltage clamping; they'd fight the intended below-ground operation. The same internal diode clamps over- and undervoltage (at reverse breakdown), so the protection strategy is keeping voltages and currents within the Absolute Maximum Ratings:
- AINxP/AINxN: AGND − 1.6 V to AVDD + 0.3 V
- Digital inputs: DGND − 0.3 V to DVDD + 0.3 V
- Continuous current, any non-supply pin: ±10 mA
Recommended operating range is tighter and gain-dependent: AGND − 1.3 V to AVDD at gains 1/2/4, and AGND − 1.3 V to AVDD − 1.8 V at gains 8–128. Size any series-R protection so fault currents stay under ±10 mA.
One more: don't over-correct in software. The part has gain and offset calibration registers that automatically apply calibrated results — do a one-time system calibration at production and program them.
How does the frame CRC work, and why does it matter?
The ADS131M02 runs a CRC engine on both directions of the SPI link, and the two halves are not symmetric. The output CRC cannot be disabled — it always appears at the end of every output frame, whether you check it or not. The input CRC is optional (RX_CRC_EN, off by default): enabling it protects your register writes and command bytes from being corrupted in transit, at the cost of a slightly longer SPI transaction.
This matters for two reasons. First, if you tie CS low in hardware because the ADS131M02 is the only device on your SPI bus (see wiring above), the datasheet requires you to enable and use the data-in/data-out CRC — CS toggling is otherwise part of how the part frames a transaction, so removing it needs the CRC as a substitute integrity check. Second, it gives you a clean way to separate a real conversion problem from a communications problem during bring-up or field debugging: if the output CRC on a frame mismatches, the fault is in the SPI link (timing, noise, a dropped bit) — not in the analog front end or the modulator. Don't spend time chasing an "analog" explanation for intermittent bad samples until you've confirmed the frame CRC is clean.
How do I verify it works?
- Power-up: after supplies reach 90%, wait for DRDY's low→high edge — that marks the end of tPOR and says the SPI interface is ready. With CLKIN toggling, the modulators start after (256 + 44) × tMOD; at default OSR 1024 / 8.192 MHz, settled data arrives within tSETTLE1 = 0.323 ms (tSETTLE3 = 0.823 ms).
- Functional check: route the internal DC test signal (2/15 × VREF, auto-scaled with gain — 160 mV at gain 1, 80 mV at gain 2) via the MUXn[1:0] bits and confirm the code matches. Critical: this test signal cannot be measured in global-chop mode — run the check in normal mode.
- Clock quality: scope CLKIN for overshoot and glitches before trusting data; glitches show up directly as conversion noise. Fix overshoot with a source-termination resistor at the clock buffer. Confirm the frequency is legal for your PWR[1:0] mode.
- Synchronization: confirm you're sampling in lockstep with DRDY and no frames drop over a long soak.
- Current-detect mode: push a stimulus past a programmed threshold and confirm the notification fires, checking the all-vs-any logic (CD_ALLCH, CHn_EN).
- Power modes: verify supply current actually changes when you switch HR/LP/VLP, and that noise matches the mode-independent tables.
It's not working — how do I triage?
In order:
- Dead ADC? Check SYNC/RESET isn't stuck low. It's active-low and dual-function: held low longer than tw(RSL) it resets, and the device stays in reset until the pin returns high. A floating or firmware-held-low pin is the classic cause.
- Noisy data? Scope CLKIN. Glitches on the clock input lead directly to noise in the conversion data; also verify the frequency is legal for the power mode.
- Intermittent bad samples? Check the frame CRC before blaming analog (see "How does the frame CRC work?" above) — a mismatch there means the SPI link, not the conversion.
- Channels read dead/all zeros? Inject the internal DC test signal — in normal mode, not global-chop — to isolate ADC vs. front end.
- Readings pinned at rail or floating? The front end likely exceeded the input range. Verify conditioning against AGND − 1.6 V to AVDD + 0.3 V (abs-max) and the recommended range at your gain. Excessively large series-R/filter values can also prevent the filter capacitor from providing enough instantaneous charge to the ADC input sampling circuit.
- Periodic missing samples / timing drift? You're probably free-running reads. Tie either SYNC/RESET or DRDY to the MCU — the datasheet warns synchronization can't be regained after a clock bit error.
That's the loop: wire it per the above, prove the signal chain with the internal test signal, trust the CRC to separate SPI faults from real data, and keep the charge pump in mind before you add any input clamps.
Part page: ADS131M02.