ADS131M02 registers — register map, bit fields and reset values

The ADS131M02 is a 2-channel, 24-bit simultaneous-sampling delta-sigma ADC with a PGA per channel, accessed over a full-duplex 4-wire SPI port. Its register space is a single flat 6-bit linear map, addresses 00h–3Fh, with no bank or page switching; every address not listed in the register map (Table 8-12) is RESERVED. Implemented registers fall into three banks: system/status and configuration (00h–06h), a per-channel calibration block (09h–12h), and the register-map CRC (3Eh). Conversion data is not in the register map at all — channel samples are clocked out on DOUT as part of the SPI data frame.

Identity and status registers: ID (00h), STATUS (01h)

ID — address 00h, read-only, reset = 22xxh.

Use as a device-ID check by verifying the upper byte reads 0x22; treat only the low byte as revision-dependent.

STATUS — address 01h, read-only, reset = 0500h.

STATUS contents are also returned automatically as the response/status word at the start of each output frame.

Mode, clock, gain and configuration registers: MODE (02h), CLOCK (03h), GAIN1 (04h), CFG (06h)

MODE — address 02h, reset = 0510h.

CLOCK — address 03h, reset = 030Eh. Note: despite the name, this register holds the power-mode selection; MODE has no power bits.

Output data rate: fDATA = fCLKIN / (2 × OSR). At the default OSR = 1024 with an 8.192 MHz clock, fDATA = 4 kSPS.

GAIN1 — address 04h, reset = 0000h. PGA gain for both channels lives here centrally, not per channel.

Full-scale range follows the internal 1.2 V reference divided by gain: gain 1 = ±1.2 V down to gain 128 = ±9.375 mV.

CFG — address 06h, reset = 0600h.

Lower bits of CFG enable the DC-block filter and comms-CRC functions; the notes do not give their individual field names or positions.

Per-channel registers: CH0_CFG (09h), CH0_OCAL_MSB (0Ah), CH0_OCAL_LSB (0Bh), CH0_GCAL_MSB (0Ch), CH0_GCAL_LSB (0Dh), CH1_CFG (0Eh), ...

Identical block repeated for CH0 and CH1 (CH1 block: CH1_CFG 0Eh, CH1_OCAL_MSB 0Fh, CH1_OCAL_LSB 10h, CH1_GCAL_MSB 11h, CH1_GCAL_LSB 12h).

CHx_CFG bit fields (reset = 0000h):

CH1_CFG mirrors this with MUX1[1:0] and its own DC-block disable bit.

Register-map CRC: REGMAP_CRC (3Eh)

Computation: enable with MODE.REG_CRC_EN = 1; polynomial selected by MODE.CRC_TYPE (0 = 16-bit CCITT, 1 = 16-bit ANSI); seed FFFFh; coverage is addresses 02h through 12h, processed MSB of 02h first through LSB of 12h. The host verifies by reading registers 02h–12h, recomputing the CRC with the same polynomial/seed/order, and comparing against REGMAP_CRC. STATUS.REG_MAP (bit 13) sets whenever the CRC value changes — including changes caused by normal register writes — so expect it after any configuration write to a covered register. Clear by reading STATUS. REGMAP_CRC reads 0000h until REG_CRC_EN is set, so no faults are flagged before the feature is enabled.

Reserved registers and warned-against values: RESERVED (05h), RESERVED (3Fh)

Two entire addresses are dedicated RESERVED registers, both R/W with reset = 0000h:

Reserved fields inside implemented registers (e.g. ID bits 15:12 and 7:0, STATUS bits 7:2) are read-only and read fixed values; they cannot be written and must not be treated as writable. Every address in 00h–3Fh not listed in the register map (Table 8-12) is RESERVED.

Additional traps the datasheet calls out:

• WREG latches as it shifts in. Registers are written as they shift in on DIN, so an input-CRC error does not prevent an erroneous value from being written — a CRC error during WREG only sets STATUS.CRC_ERR; the bad value is already latched.
• WREG framing. Command word is 011a aaaa annn nnnn (address + count−1); each register's data must be MSB-aligned in its own word. If input CRC is enabled, write the input CRC after the register data.
• RESET command (0011h) requires a full frame. It is not latched until the whole frame completes; terminating early discards it. After reset, wait t_REGACQ (≤ 5 µs) before communicating again. There is no register write that triggers a reset. Note that the SPI RESET command is not the only reset path: the device also resets via the dual-function active-low SYNC/RESET pin (held in reset while the pin is low longer than t_w(RSL), released when it returns high) and via power-on reset (POR) when a valid supply is first applied.
• LOCK interface. Once locked, only NULL, RREG, and UNLOCK commands are accepted; WREG and all other state-changing commands are ignored. STATUS.LOCK (bit 15) reads 1 while locked.
• Read-only registers. ID (00h) and STATUS (01h) are entirely R.
• No explicit register write-ordering requirements beyond the frame and CRC rules above are documented.

Accessing the registers: RREG, WREG, NULL, RESET

Registers sit in one flat 6-bit address space (00h–3Fh) addressed via SPI command words on a 4-wire full-duplex slave port (CS, SCLK, DIN, DOUT). There is no bank/page select register.

• Single-register access uses count = 000 0000b.
• RREG burst: the device shifts out all requested registers MSB-aligned, ascending address order. ADC conversion data is NOT output in the frame following a multi-register RREG — keep toggling SCLK to drain the register stream.
• WREG burst: data words follow the command word immediately, MSB-aligned; registers latch as they shift in (see the CRC caveat above).
• Conversion data is not a register read: each frame on DOUT carries the status/response word, CH0 data, CH1 data, and a data CRC word. Word width is set by MODE.WLENGTH (default 24-bit); in 16-bit word mode the 8 fine LSBs are truncated.

Key timing constraints: SCLK period ≥ 40 ns (≤ ~25 MHz; ≥ 64 ns when DVDD is 1.65–2.0 V), DIN setup/hold 5/8 ns, SPI timeout 32768 · tCLKIN, t_REGACQ ≤ 5 µs after reset, tPOR typ 250 µs to first DRDY rising.

Part page: ADS131M02.