ADS131M02 configuration: startup sequence for a dual-channel energy-meter front-end

ADS131M02: what is the typical use case this sequence targets?

A class 0.1 single-phase electricity meter front-end: the ADS131M02 samples the mains line synchronously on both channels — channel 0 digitizes line current from a current transformer (CT), channel 1 digitizes line voltage from a resistor divider. Both channels sample simultaneously so the phase relationship between V and I is preserved, which is what lets downstream firmware compute real power and energy correctly. The design parameters from the datasheet's typical application:

ADS131M02: what must be true before the first register write?

Two prerequisites, both stated by the app note:

1. Master clock: drive 8.192 MHz into CLKIN. That is the nominal HR-mode frequency; the Recommended Operating Conditions table gives the HR-mode fCLKIN range as 0.3 MHz (min) to 8.4 MHz (max), so 8.192 MHz is in spec.
2. SPI mode: CPOL=0, CPHA=1 at 8.192 MHz. HR mode on this part requires that SPI polarity.

The datasheet does not state a required wait between power-up and the first register write beyond what is listed below, and the app note simply says "when powered on, the MCU configures the registers using SPI register writes." No NULL/handshake frame is documented as a prerequisite for the first write.

ADS131M02: what is the startup sequence, step by step?

The app note describes the settings in words; the exact 16-bit values below are derived from the register field tables (the datasheet does not print them verbatim). The order matches the app note's sequence.

1. GAIN1 (Addr 4h) = 0x0000 — PGA gain of 1 on both channels. The e-meter app runs unity gain on the CT and voltage-divider inputs.
2. CH0_CFG (Addr 9h) = 0x0000 — channel 0 input mux to the external ADCINP0/ADCINN0 pins, phase delay 0. 0x0000 is also the reset value, so this asserts the default external-input + zero-phase condition.
3. CH1_CFG (Addr Eh) = 0x0000 — same for channel 1.
4. CLOCK (Addr 3h) = 0x030A — the only non-default write. The app note requires OSR = 512, both channels enabled, HR mode. From the CLOCK field table (reset = 0x030E):

Changing OSR from the 1024 default (011) to 512 (010) clears bit 2 (0x0004), giving 0x030A.

After the CLOCK write the part is converting. The MCU then enables a GPIO interrupt on the falling edge of DRDY to pick up new samples.

ADS131M02: which writes are required, and which are design choices?

Fixed requirement: CH0_EN and CH1_EN both = 1. The whole use case is measuring line current on one channel and line voltage on the other simultaneously; disabling a channel would break the energy computation.

Design choices, with the trade-off the datasheet states:

• GAIN1 = 0x0000 (gain = 1). Gain is per-channel and selectable (1/2/4/8/16/32/64/128). The stated trade-off: full-scale range scales inversely with gain, FSR = ±1.2 V/Gain — so gain 1 gives ±1.2 V, gain 8 gives ±150 mV, gain 128 gives ±9.375 mV. Higher gain buys LSB resolution on small signals but shrinks headroom before clipping. Additionally, at gain ≥ 8 the PGA switches to a precharge-buffer input, changing the input structure from a resistive load (330 kΩ · 4.096 MHz / f_MOD) to a very-high-impedance, bias-current-specified input — which matters for how your CT or divider source loads the pin. This design keeps gain 1 for ±1.2 V of headroom across the 0.05–100 A CT swing.
• CLOCK OSR = 512. Default is 1024 (OSR[2:0] = 011); the app note deliberately drops it to 512. OSR sets the amount of modulator-output averaging and therefore the filter bandwidth: lower bandwidth → lower noise, higher bandwidth → higher noise. Since OSR = f_MOD / f_DATA, choosing 512 trades some noise performance for a higher output data rate (8 kSPS at the 8.192 MHz clock) — faster sample delivery to the metrology firmware within the 50/60 Hz window.
• PWR[1:0] = HR mode. Three power modes exist — HR, LP, VLP — allowing scaling of power with bandwidth and performance. HR is the reset default, so no write was strictly needed to enter it; LP/VLP would be chosen only if the power budget dominated. Note the coupling: CLKIN frequency must be scaled in conjunction with the power mode (LP nominal 4.096 MHz, VLP nominal 2.048 MHz).
• CH0/CH1_CFG phase-delay bits = 0. The phase-delay field is a hardware phase-alignment option; this design sets 0 and performs phase calibration entirely in software. Choosing 0 vs. a nonzero phase value is a real filter/phase-timing choice.

ADS131M02: what delays or ready-flag polls are required between steps?

• Between consecutive SPI register writes: none. The datasheet imposes no inter-write settle delay; back-to-back register writes are fine.
• After any write that changes the signal chain (channel enable, mux, gain, OSR, or a resynchronization event), the digital filter must settle. The sinc filter requires time to settle after these events, and the ADC does not gate unsettled data — the datasheet states the host must account for the settling time and disregard unsettled data if any are read. Table 8-3 gives settling time in tCLKIN cycles per OSR; for this design's OSR = 512 it is 1624 tCLKIN ≈ 198 µs at 8.192 MHz (1624 / 8.192 MHz). For reference: OSR 64 → 728, 128 → 856, 256 → 1112, 1024 → 2648, 8192 → 16984, 16384 → 33368 tCLKIN. The ready-flag pattern is: wait until the settling time has elapsed, then take the data at the next DRDY falling edge after it expires — anything in between is invalid. (A separate "fast startup" table, Table 8-8, exists but is scoped to the default OSR = 1024 and does not apply here.)
• Read-timing constraint: the DRDY pulse is blocked when new conversions complete while conversion data are being read. Avoid reading ADC data during the time where new conversions complete, in order to achieve consistent DRDY behavior — schedule the SPI read so it does not straddle the next conversion-complete point.

ADS131M02: how does firmware read the results back?

Trigger: the part signals new conversion data on the DRDY output. With two channels there is one shared signal; the reference design configures a GPIO interrupt on the falling edge of DRDY, which indicates new samples are available. Polling DRDY's level is equally valid, just not what the reference design does.

Frame: on DRDY, clock out one fixed SPI frame: 1 status word + 2 data/register words (+ optional CRC word). In HR mode at the default 24-bit word length this is the 24-bit STATUS word followed by two 24-bit channel data words (ch0 then ch1). Each channel's conversion is 24-bit signed, two's-complement, MSB-first. Word size is configured by MODE.WLENGTH[1:0], defaulting to 24 bits; at a 16-bit word size the data LSBs are truncated, and at 32-bit the LSBs are zero-padded or MSBs sign-extended.

STATUS register (Addr 1h, reset = 0500h) — readable directly, and automatically output as the response to the NULL command:

The DRDY0/DRDY1 bits are the per-channel "new data available" indicators; WLENGTH[9:8] lets firmware confirm the frame size it expects. If CRC is enabled, validate the CRC word and check STATUS.CRC_ERR to catch a corrupted transfer.

One timing detail: when each channel's data becomes available relative to DRDY is set by the channel phase-calibration setting and the DRDY_SEL-type config. This design keeps phase delay 0 and reads both live words in one frame, so a single DRDY interrupt yields both V and I samples together — which is what the energy computation needs.

ADS131M02: how does firmware verify the configuration took?

Three levels, from per-register read-back to a full-map checksum:

Level 1 — RREG read-back of each written register. Use the RREG command, format 101 aaaaa nnnnnn (address + number-of-words − 1), to read each register and compare against the intended value:

Level 2 — STATUS health check. Read STATUS and confirm: LOCK = 0, REG_MAP = 0 after read-back (it is set by register writes and cleared by reading STATUS or a NULL response), CRC_ERR = 0, WLENGTH[9:8] = 01 (24-bit), and DRDY1/DRDY0 going high — which proves both ADCs are actually converting, not just written.

Level 3 — REGMAP_CRC (Addr 3Eh) full-map checksum. The device continuously computes a 16-bit CRC of the whole register map (one map bit per CLKIN period) and exposes it in REG_CRC[15:0]. Read REGMAP_CRC, independently compute the same 16-bit CRC over the register map you intended, and compare. A match means the on-chip register map is exactly what you intended; a mismatch means a write silently failed or landed in the wrong field. This is the strongest single check because it detects an unwanted change in any mapped bit, not just the registers you touched.

ADS131M02: what register-level mistakes break this design?

1. Power-mode ↔ CLKIN mismatch. PWR[1:0] selects HR/LP/VLP, but the external clock frequency must follow the Recommended Operating Conditions for the chosen mode for the device to perform according to specification. 8.192 MHz and HR are a matched pair; switching to LP/VLP without rescaling the clock is out-of-spec.
2. Disabling a channel you need. Clearing CH0_EN or CH1_EN leaves that channel's STATUS DRDY bit at 0 and silently breaks the power/energy math.
3. Input-CRC enabled but computed wrong. If RX_CRC_EN is set and the CRC word doesn't match, the device executes no commands except WREG — reads and NULL frames do nothing, CRC_ERR is set, and the next frame responds as if it were a NULL. The asymmetry: WREG always executes even when the CRC check fails, so the symptom is "my reads stop working, my writes still land."
4. Word-length mismatch. If WLENGTH and the MCU's SPI frame length disagree, the status/data words shift and every value decodes wrong — not just a precision loss.
5. Forgetting to clear REG_MAP. It is set whenever the register-map CRC changes (including from register writes) and stays set until STATUS is read. If never cleared, a spurious "map changed" condition keeps reporting and can hide real faults.
6. Reading unsettled data after a signal-path change. The device does not gate unsettled data; discard samples until the next DRDY edge after the 1624 tCLKIN settling time expires.
7. Writing reserved/read-only bits. Several bits are marked "Reserved – always write 00b" (e.g. CLOCK[7:6]) and some fields are read-only; nonzero writes there produce undefined register behavior.

ADS131M02: what data rate does this configuration produce, and does it meet the metering requirement?

fDATA = 8 kSPS: f_MOD = f_CLKIN/2 = 4.096 MHz, and OSR = f_MOD / f_DATA, so f_DATA = 4.096 MHz / 512 = 8000 SPS, matching the datasheet's OSR/data-rate table for 8.192 MHz, HR, OSR=512. That is 160 samples per 50 Hz line cycle and ≈133 per 60 Hz cycle — far above Nyquist for the line fundamental and its harmonics. The ~198 µs filter settling time is negligible next to the ~20 ms line period, so it does not disturb the metering cadence.

Part page: ADS131M02.