ULN2003 Motor & Stepper Driver: Saturation Drop, Duty-Cycle Derating, and COM Clamp Wiring

September 21, 2026 · AI-generated from the datasheet, fact-checked by two independent LLM critics

The ULN2003 is a seven-channel high-voltage, high-current Darlington transistor array — seven open-collector switches in one package, each rated 500 mA continuous collector current (600 mA peak) and 50 V output capability, with integrated clamp diodes for inductive loads. It's the classic logic-to-load interface: drive the inputs from 5 V TTL or CMOS logic, and the outputs sink relays, solenoids, DC motors, LED displays, filament lamps, thermal printheads, or the windings of a small unipolar stepper motor. If you've bought a "stepper driver board ULN2003" module — the little blue board paired with a 28BYJ-48 stepper — this is the IC on it. The inputs are pinned opposite the outputs specifically to simplify PCB layout, and outputs can be paralleled for higher current.

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Start building with ULN2003 → This guide comes from the same grounded, cited datasheet answers — ask the assistant your own ULN2003 questions.

The part is easy to use and just as easy to misuse, because the numbers that constrain a design aren't the headline ones. Below is what each datasheet figure actually means on the bench, followed by wiring, testing, and troubleshooting.

The ULN2003 numbers engineers misread

Saturation voltage is not zero. The Darlington output drops real voltage when it's on. The datasheet specifies VCE(sat) as typ 0.9 V / max 1.1 V at 100 mA, typ 1.1 / max 1.3 V at 200 mA, and typ 1.3 / max 1.6 V at 350 mA. Budget roughly 1–1.6 V of drop into any load-voltage calculation: a 5 V relay coil driven through a ULN2003 sees maybe 3.5–4 V, not 5 V. If your load "seems weak" by about a volt and a half, that's the switch drop, not a fault — and it's also where most of the part's heat comes from.

The 500 mA headline is not a per-channel entitlement at all duty cycles. The 600 mA peak figure in the Features line carries no defined pulse width or duration. What the datasheet gives instead is a pair of "Peak collector current vs. duty cycle" curves (Fig. 17 for DIP-16, Fig. 18 for SO-16), evaluated at 70 °C ambient and parameterized by the number of simultaneously active outputs. The rule both curves state and plot is that allowed per-channel current decreases as more outputs are active at once. The approximate graph reads: on SO-16 at 100% duty, two active outputs allow ~200 mA each, five active ~120 mA, seven active ~80 mA. On DIP-16 the same rule holds — at ~50% duty the curve reads ≈450 mA with two active outputs versus ≈300 mA with seven. Allowed current collapses with both higher duty cycle and more outputs on at once, and the SO-16 is the more restricted case. Use those curves, not the headline number, when sizing real loads.

Datasheet caveat: these duty-cycle figures are typical graph reads, given only at 70 °C ambient — there is no tabulated derating table and no condition detail beyond that. The datasheet also never reconciles these curves with the separate RthJA/TJ-max thermal route below; when the two limits disagree for your conditions, apply the more conservative one.

Thermal is the failure mode that actually bites. RthJA is 70 °C/W for the DIP-16 and 120 °C/W for the SO-16, with a 150 °C max junction and −40 to 85 °C operating ambient. Run the arithmetic: at 300 mA with ~1.5 V of saturation drop, each active channel dissipates ~0.45 W. On SO-16 at 25 °C ambient, one channel at 300 mA lands at ~79 °C junction, two channels at ~133 °C, and three channels at ~187 °C — already past the 150 °C limit. There is no published power-derating-vs-ambient curve in the datasheet; you derive allowable dissipation yourself from Pmax = (TJmax − Tamb)/RthJA. For multi-channel or heavy loads, use the DIP-16, derate currents, or offload to external power handling.

Input thresholds hang by logic-family margins. The ULN2003 is the 5 V TTL/CMOS variant of the family (ULN2001 general-purpose, ULN2002 for 14–25 V PMOS, ULN2004 for 6–15 V CMOS/PMOS). Its guaranteed on-state input voltage is max 2.4 V at 200 mA, 2.7 V at 250 mA, and 3.0 V at 300 mA — and 2.4 V at 200 mA is the lowest current at which the on-state input voltage is specified; no VI(ON) threshold is tabulated below 200 mA (other parameters, like VCE(sat) at 100 mA, do appear in the same table). A genuine TTL output whose VOH only guarantees ~2.4 V sits right at the 200 mA edge with no margin for heavier loads. A 3.3 V MCU GPIO clears the 2.4 V threshold comfortably at 200 mA, but at 250–300 mA it sits at or below the 2.7 V and 3.0 V thresholds — a real 3.3 V GPIO's guaranteed VOH may not even reach 3.0 V — so for heavy loads don't count on full saturation from a bare GPIO; whether your particular output guarantees the needed high level is a property of your MCU, not this datasheet. For heavy loads from marginal drivers, add series drive or a small driver stage.

The input draws current, not just voltage. The input is internally base-driven through a 2.7 kΩ series resistor (with a 7.2 kΩ base-emitter and 3 kΩ base-collector resistor per the datasheet schematic), so the input sinks current into the pin and the driving pin must source typ 0.93 mA / max 1.35 mA at VI = 3.85 V, and up to 1.45 mA at VI = 12 V. A weak source that can supply voltage but not that current won't fully saturate the channel. Input capacitance is 15 pF typ / 25 pF max — negligible loading.

Off-state currents exist on both sides. With the input held low, the channel draws off-state input current of min 50 µA / typ 65 µA — your low-side driver must sink that to hold the channel off. With the channel off, output leakage can reach 50 µA at VCE = 50 V (100 µA at 85 °C). Fine for coils and lamps; on a high-impedance load, budget for it.

Wiring the ULN2003 into your design

The topology is open-collector and inverting: outputs sink to ground, the load connects from the positive supply rail to the output pin, and input high means output low. There is no high-side capability here — the load must sit between the rail and the chip.

Concretely, per the datasheet pinout: inputs IN1–IN7 are pins 1–7, GND is pin 8, COM is pin 9, and outputs OUT1–OUT7 are pins 10–16. So a relay coil ties from the load supply rail to OUT1 (pin 10), driven from IN1 (pin 1), with GND (pin 8) to logic ground. On the 28BYJ-48 stepper, each of the four phase coils ties from the 5 V rail to OUT1–OUT4 (pins 10–13), driven from IN1–IN4 (pins 1–4), sequenced one phase at a time.

For anything inductive — relay coil, solenoid, motor winding, stepper phase — tie pin 9 (COM) to the load's supply rail. Each output has an integrated clamp diode common-cathode to COM; with COM tied correctly, the coil's flyback spike is caught at roughly Vload + VF, where the clamp diode's forward drop is typ 1.7 V / max 2.0 V at 350 mA. No external flyback diode is then needed on the output. Leave COM floating or at the wrong level and the clamp does nothing: the collector flies up toward the 50 V absolute-max rating on every turn-off, which is the most common way this part dies.

On the input side, you generally don't need external pull-downs: the internal 7.2 kΩ base-emitter resistor biases each input toward ground, so a floating input self-turns off. If you drive from an open-collector source instead of a push-pull logic pin, size the pull-up so it can source the ~1–1.5 mA input current and hold the input above the on-threshold for your load current (2.4 V at 200 mA, 2.7 V at 250 mA, 3.0 V at 300 mA). Keep input voltage within the 30 V abs-max and continuous base current within 25 mA.

Two more practical points. First:

Bench practice, not datasheet spec: the datasheet specifies no decoupling value and no derating curve beyond RthJA. As practice, put a small local cap near the load-supply/COM pins, since the clamp diodes dump coil energy through COM.

Second, for stepper duty: the ULN2003's switching delays are typ 0.25 µs, max 1 µs — entirely adequate for relays, solenoids, and low-speed stepper sequencing, but not for high-frequency PWM. If your design switches at high kHz, this is the wrong part, not a defective one.

Testing the ULN2003 on the bench

Run these in order — drive, outputs, leakage, clamp, in-circuit, thermal — so a failure isolates to the right stage:

Input drive. Apply VI = 3.85 V to an input and measure the source current: expect typ 0.93 / max 1.35 mA. Ramp the input up and confirm the channel turns fully on by the thresholds: 2.4 V at 200 mA, 2.7 V at 250 mA, 3.0 V at 300 mA. Drive the input low and confirm it draws min 50 µA / typ 65 µA with the channel off.
Saturation. Load each channel at 100 / 200 / 350 mA and measure VCE(sat): it must be ≤ 1.1 / 1.3 / 1.6 V respectively (typ 0.9 / 1.1 / 1.3 V). A reading well above max means a weak or damaged driver, or insufficient input drive.
Off-state leakage. With inputs off, apply VCE = 50 V and check leakage ≤ 50 µA (≤ 100 µA at 85 °C).
Clamp diode. Forward-bias COM→output at IF = 350 mA: VF should be typ 1.7 / max 2.0 V. Reverse it at VR = 50 V: leakage ≤ 50 µA.
In-circuit inductive check. Cycle a real relay or solenoid and scope the collector at turn-off: the spike must clamp to roughly Vload + VF and never exceed 50 V. This is the definitive test that pin 9 is actually tied to the load rail. Also confirm switching times of typ 0.25 µs / max 1 µs.
Thermal. Compute each channel's dissipation as measured VCE(sat) × I, sum the channels, and apply RthJA (70 °C/W DIP-16, 120 °C/W SO-16). Stay under 150 °C junction / 85 °C ambient, and spot-check with a thermocouple. This is the step most real boards fail.

Throughout, keep inputs below 30 V, and hold per-channel current to whichever is lower: the 500 mA absolute maximum, or what the duty-cycle curve allows for your duty and active-channel count. On multi-channel loads the curve is almost always the binding limit, not the 500 mA. Don't leave a shorted load energized during soak tests.

Troubleshooting the ULN2003

Output won't pull fully on. Compare your actual logic-high voltage against the on-thresholds (2.4 V @ 200 mA, 2.7 V @ 250 mA, 3.0 V @ 300 mA). A weak 3.3 V or marginal TTL drive into a 250–300 mA load never fully saturates. Driving harder normally fixes it. If the load is merely ~1–1.6 V short of the rail with everything else healthy, that's the specified VCE(sat), not a fault.
Output stays on when the input is driven low. The input draws min 50 µA / typ 65 µA off-state; if your low-side driver can't sink that firmly, the input floats up into the on region. Verify the input is actually pulled near 0 V.
Channel "leaks" when off. Up to 50 µA of output leakage at VCE = 50 V (100 µA at 85 °C) is normal. On a high-impedance load it can look like failed switching — check that the load current is well above this leakage floor rather than chasing the 50 µA.
Inductive load glitches or the part dies repeatedly. The most common root cause is pin 9 (COM) not tied to the load supply rail. Scope the collector during turn-off: it should clamp to Vload + VF (clamp VF typ 1.7 / max 2.0 V) and never exceed 50 V.

Not in the datasheet: the datasheet specifies only VF and leakage for the clamp diode — there is no avalanche or flyback-energy-per-pulse rating. For large, high-energy windings, verify clamp current and dissipation yourself rather than assuming a surge spec exists.
Runs hot. Recompute dissipation against RthJA (70 °C/W DIP-16, 120 °C/W SO-16) and the 150 °C junction limit. With several channels at 300 mA+ the SO-16 runs hot fast — derate or switch packages.
Won't switch fast enough. Not a fault: delays are typ 0.25 µs / max 1 µs by spec. It's built for relays, solenoids, lamps, and steppers, not high-frequency switching.
Nothing works at all. Check pinout first: inputs are pinned opposite the outputs, and a swapped input/output assignment is a very common mistake. Anything that repeatedly fails has likely exceeded a hard limit at some point — 500 mA per channel (less wherever the duty-cycle curves bind), 30 V input, 50 V output — so remove any shorted or overloaded condition before continuing to test.

One note on part numbering for anyone arriving from a "motor driver ULN2003A" or "ULN2003AN" search: within ST's nomenclature, ULN2003A is simply the DIP-16 order code of the same device — the SO-16 variant carries the -D1 suffix (e.g. ULN2003D1) — so it is not a different part. The -AN suffix is TI's DIP package designation for its equivalent device; electrically these are all the 5 V TTL variant described here. And if you need to drive two motors, that's two chips (or two of the common blue breakout boards), one stepper or DC motor per set of channels — there is no single-chip two-motor mode.

One caveat on paralleling: the datasheet explicitly sanctions paralleling outputs for higher current but gives no current-sharing guidance, no ballast-resistor recommendation, and no per-channel balance spec. Channels share a common emitter and don't inherently balance, so design headroom — not a datasheet rule — has to cover the imbalance, and the duty-cycle/active-output curves still apply to the combined load.

Part page: ULN2003.