From the bench

UC3843BN: Q&A on the Current-Mode PWM Controller with the Low UVLO Window

August 8, 2026 · AI-generated from the datasheet, fact-checked by two independent LLM critics

The UC3843BN is a current-mode PWM controller for switching power supplies, packaged in a Minidip-8, that drives an N-channel MOSFET directly from a totem-pole output stage built to source or sink high peak current. Its defining characteristic within the UC384xB family is a low undervoltage-lockout window: it starts at a typical 8.4 V (min 7.8 V, max 9.0 V) and keeps running down to a typical 7.6 V after turn-on, in contrast to the UC3842B/UC3844B siblings whose 16 V-on/10 V-off window the datasheet flags as ideally suited to off-line applications. That makes the UC3843BN the natural pick for DC-DC converters fed from low or intermediate voltage buses. It also runs to duty cycles approaching 100% (max duty typ 96%, min 94%), with no internal toggle flip-flop capping it near 48% like the 3844B/3845B variants. The oscillator is guaranteed at 250 kHz, with current-mode operation specified to 500 kHz. If you're building a boost, flyback, or forward converter where the supply rail is modest and you need full duty-cycle range, this is the part of the family aimed at you.

Next step
Start building with UC3843BN → This guide comes from the same grounded, cited datasheet answers — ask the assistant your own UC3843BN questions.

The rest of this post is structured as the questions you'd actually ask when bringing the UC3843BN into a design: what it's for, how to wire it, what will bite you, how to prove it works on the bench, and why it might be misbehaving.

What is the UC3843BN actually for, versus its siblings? (Which use cases is the UC3843BN intended for?)

The datasheet grades the UC384xB family explicitly, and the UC3843BN sits in a specific slot:

One practical note the datasheet asserts less explicitly: the low 8.4 V start threshold is what practically suits this part to DC-DC converters on low/intermediate buses, while the off-line statement is reserved for the 16 V parts.

How do I integrate the UC3843BN into a design? (Wiring, oscillator, and bias supply)

Three design areas matter most: the oscillator timing, the start-up bias, and the gate-drive interface.

Oscillator: pick RT/CT from the part's own curves. The datasheet's Figure 2 (Timing Resistor vs. Oscillator Frequency, Vi = 15 V, TA = 25 °C) gives concrete anchors:

In short, you have two knobs and one frequency target, and the trade-off between them also sets your maximum duty cycle: the Maximum Output Duty Cycle vs. Timing Resistor curve (Figure 5) is where you confirm the duty headroom at your chosen RT. The Current Sense Threshold vs. Error Amp Output curve (Figure 7) shows the same relationship from the other side — for example, RT = 2 kΩ gives D_max ≈ 60–70% and RT = 5 kΩ gives ≈ 82–92%, depending on the 7.5 vs 8.8 mA discharge-current curve (Vi = 15 V, CT = 3.3 nF, TA = 25 °C). Check both before committing to a layout.

Start-up bias: budget around the UVLO window and the supply currents. The electrical-characteristics table gives you the numbers that shape the VCC start-up network:

The design consequence: during the pre-start phase the part draws well under 0.5 mA, so a start-up resistor feeding the VCC capacitor can be large enough to charge to the 8.4 V threshold without burning much idle power. Once switching begins, the auxiliary winding must supply the 12–17 mA operating current and hold VCC above the ~7.6 V turn-off point. Size the hold-up so transients on the aux rail don't dip below that.

Gate drive: respect the output stage ratings. The output delivers VOH typ 13.5 V (min 13 V) at 20 mA source and typ 13.5 V (min 12 V) at 200 mA source; VOL is typ 0.1 V / max 0.4 V at 20 mA sink and typ 1.6 V / max 2.2 V at 200 mA sink. Rise and fall times are typ 50 ns (max 150 ns) with CL = 1 nF. Size the external gate resistor so peak gate-charge current stays within the 200 mA-class source/sink ratings given those ~50 ns edges — a direct-drive MOSFET with a large gate charge will pull harder than the output is rated for, and the energy delivered into a capacitive load is separately capped (see the next section).

What will bite me? (Critical limits and parameter sensitivities of the UC3843BN)

The absolute maximum ratings — all voltages referenced to pin 5 — are the hard walls:

The headline numbers to carry in your head: VCC on a stiff rail stays under 30 V, the pin 2/3 analog inputs stay within −0.3 to 5.5 V, output current within ±1 A, and the Minidip thermal budget is 1.25 W.

Beyond the absolute limits, two parameter sensitivities deserve bench attention across your full operating range:

How do I verify the UC3843BN on the bench? (Testing and verification procedure)

A short, ordered bench sequence proves the part is what you think it is and behaves as specified.

1. Verify the UVLO thresholds — the signature check. With pin 5 grounded and pins 2 and 3 held at 0 V, slowly ramp VCC (pin 7) from 0 V up through ~10 V while watching the output. The part must stay off until VCC crosses the ~8.4 V start threshold (output low, saturating near 0.1 V / 1.1 V max at 1 mA sink per the VOLS spec at VCC = 6 V), then begin switching. Ramp VCC back down: it must keep running until ~7.6 V, confirming the hysteresis. Measure both transition points and confirm they sit inside the min/max windows (7.8–9.0 V start, 7.0–8.2 V turn-off). This is the single most effective "is this really a UC3843BN and not a 3842/3844" sanity check, since the 842B/844B parts start at ~16 V.

2. Verify frequency and duty-cycle capability. Measure the output frequency against your RT/CT target, and confirm maximum duty approaches the ~96% typical figure rather than the ~48% you'd see on a toggle-limited 3844B/3845B variant.

3. Check slope compensation at high duty. Because this part runs above ~50% duty, current-mode control needs slope compensation to stay stable — which is precisely why the datasheet documents an application circuit for it: the "Isolated MOSFET Drive and Current Transformer Sensing" circuit (Figure 19) shows two slope-compensation variants feeding pin 3 (ISENSE), one with an external slope resistor and one with an internal transistor for automatic slope compensation. Use that topology as your starting point; the exact slope magnitude is a loop-design value, not a datasheet constant.

4. Verify cycle-by-cycle overcurrent behavior. The part provides "latching PWM for cycle-by-cycle current limiting," and the current-sense input on pin 3 terminates the output switch conduction; the Current Sense Circuit figure (Figure 17) documents a sense resistor Rs monitoring inductor current feeding the comparator. On the bench, drive the output into a short and verify each PWM cycle terminates when the pin-3 sense voltage reaches the comparator threshold — the pulse width pulls back cycle-by-cycle rather than the part latching off and staying off (which would instead suggest UVLO collapse). Confirm it returns to normal regulation once the fault is removed.

5. Watch supply current throughout. A healthy unit draws less than 0.5 mA in UVLO lockout and 12–17 mA once switching. An out-of-family reading is a quick flag that something is wrong before you dig deeper.

Known limitation: the exact current-sense comparator trip threshold voltage is not stated in the datasheet segments covered here, so size Rs against the comparator threshold using the datasheet's Figure 17 setup rather than a quoted number from this post.

Why is my UC3843BN circuit misbehaving? (Troubleshooting)

When a UC3843BN converter misbehaves, the failure usually traces back to one of the limits or sensitivities above. Work through these in order:

Part page: UC3843BN.