The TJA1051T is a high-speed CAN transceiver from NXP — the physical-layer chip that sits between your CAN protocol controller and the two-wire differential bus. It implements ISO 11898-2:2016 and SAE J2284-1 to −5, supports CAN FD with fast-phase timing guaranteed to 5 Mbit/s, runs from a 4.5–5.5 V VCC, and is AEC-Q100 qualified for 12 V and 24 V automotive networks. It is explicitly intended for nodes that do not need a standby mode with bus wake-up — if your node has to sleep and be woken by bus activity, this is the wrong part. Everything below is drawn from the part's own datasheet, focused on the numbers that actually constrain a design rather than the ones people skim past.
The single biggest source of confusion with this family is that "TJA1051T" is not one part. It's a family of pin-compatible variants that differ on pin 5 and on how the logic supply is handled, and those differences change what MCU you can use and what your schematic must look like.
The TJA1051T variant trap: pin 5, VIO, and EN
The SO8 pinout is TXD=1, GND=2, VCC=3, RXD=4, pin 5 (variant-dependent), CANL=6, CANH=7, S=8. What changes is pin 5:
| Variant | Pin 5 | VIO | Off mode |
|---|---|---|---|
| TJA1051T (base) | n.c. | internally tied to VCC | no |
| TJA1051T/E | EN | internally tied to VCC | yes |
| TJA1051T/3, TK/3 | VIO | external, 2.8–5.5 V | no |
In prose: the base TJA1051T leaves pin 5 unconnected and references all logic thresholds to VCC, so it only works with 5 V-logic controllers; the /3 variant brings VIO out so you can interface directly with 3 V MCUs; the /E variant adds an EN pin for a low-current Off mode. This is the fact behind the search traffic around the Adafruit CAN Pal breakout, which uses the TJA1051T/3 precisely because its VIO pin lets it pair with 3.3 V boards.
Three consequences worth internalizing:
- On the base part, a 3.3 V MCU driving TXD or S is out of spec. Logic inputs need VIH ≥ 0.7·VIO and VIL ≤ 0.3·VIO, and VIO = VCC (4.5–5.5 V) here. A 3.3 V high can fall below 0.7·VCC — the classic "the scope shows the line toggling but the part never responds" trap. There is no level-shifting inside the base part; if your MCU is 3.3 V, use the /3.
- On the base part, don't wire pin 5 to anything. It's n.c. — connecting it to VCC or ground does nothing useful on the base part and becomes a real fault the moment someone BOM-rotates in a /3 (where pin 5 is VIO) or an /E (where it's EN). Pin 5's meaning changing under the same footprint is the trap to document on your schematic.
- The base part has no Off mode. EN exists only on the /E. Your lowest-power active state on the base part is Silent mode (S = HIGH): transmitter disabled, receiver alive, bus pins released recessive. For deeper power-down you must cut VCC externally — which is safe, because an unpowered TJA1051T presents ideal passive behavior, zero load on the bus.
Wiring the TJA1051T into your design
Termination: 60 Ω differential is the operating point, not a suggestion. The datasheet specifies differential output voltage of 1.5–3.0 V with RL = 45–65 Ω, and all dynamic timing is tested at RL = 60 Ω — two 120 Ω resistors, one at each end of the line, per ISO 11898. Every level you measure is meaningless without correct termination. If you use split (common-mode) termination, the datasheet's transmitter-symmetry measurement used CSPLIT = 4.7 nF as the reference split capacitor.
Don't add pull-ups or pull-downs you don't need. The fail-safe design already handles floating pins: TXD has an internal pull-up to VIO (so it idles recessive on its own), and S has an internal pull-down to GND (so a floating S defaults the part to Normal mode). Driving TXD low pulls about 150 µA typ through that pull-up — small, but confirm your MCU can sink it. S draws only ~4 µA typ, so a 10 kΩ+ external pull resistor is fine if you want a stronger defined state, but it's never needed just to establish the default. Note the asymmetry: because S pulls down, a node that must power up in Silent mode needs you to actively drive S high — the internal bias won't do it for you.
RXD needs nothing. It's a push-pull output with roughly −3 mA typ source and 5 mA typ sink capability — it drives any CMOS input directly, no buffer, no pull-up.
Decoupling: the datasheet specifies no capacitor value. What it does specify is the current you're decoupling against: ICC is 5 mA typ / 10 max in recessive, 50 mA typ / 70 max in dominant, and up to 110 mA max with a shorted bus while driving dominant. The margin math is unforgiving: operating VCC min is 4.5 V and the worst-case undervoltage trip is also 4.5 V, so a supply sitting at the bottom of its range has zero droop budget before the transceiver disengages. Size the local ceramic plus bulk to hold VCC above that window through a ~110 mA transient, and place the ceramic physically tight to the VCC/GND pins — a correct value far away does nothing for a sub-microsecond edge.
Known limitation: the datasheet does not publish a recommended decoupling capacitance, the exact overtemperature shutdown junction temperature Tj(sd), or its hysteresis. The sizing above is derived from the datasheet's own 110 mA worst-case current and 4.5 V worst-case UV trip, not from a stated NXP recommendation.
The numbers engineers misread
The undervoltage trip is a window, and it overlaps your operating range. Vuvd(VCC) is specified 3.5–4.5 V — no typical given, so you must design against the whole band. If VCC sags anywhere in that window, the transceiver switches off and disengages from the bus at zero load until the rail recovers. That's a feature (a browning-out node removes itself instead of holding the bus down) but also a failure mode: transient droops during dominant bursts can silently drop your node off the network. On the base part there's only one rail to worry about, since VIO = VCC internally; the /3's VIO has its own trip at 1.3/2.0/2.7 V (min/typ/max).
The TXD dominant time-out sets your minimum bit rate, not your maximum. tto(dom) is 0.3 ms min / 1 ms typ / 5 ms max. Against a 5 Mbit/s CAN FD bit time of 200 ns, even the worst-case 0.3 ms timeout is 1500 bit times — it will never fire on legitimate traffic. The real constraint is the slow end: the datasheet explicitly ties this feature to a minimum bit rate of 20 kbit/s. Below that, a long dominant bit could outlast the timeout and get truncated. Keep your nominal bit rate at or above 20 kbit/s.
The logic pins are the fragile side; the bus pins are armored. Abs-max on CANH/CANL is −58 to +58 V (differential ±27 V), with transient survivability of pulse 1 −100 V, 2a +75 V, 3a −150 V, 3b +100 V, and ±8 kV ESD (IEC 61000-4-2 and HBM). Every other pin — TXD, RXD, S, GND, VCC, VIO — is limited to −0.3 to +7 V with ±4 kV ESD. In practice, parts damaged on the bench die on the logic side, not the bus side: be careful probing TXD and RXD. The driver itself is current-limited on dominant (CANH −70 mA typ, CANL +70 mA typ), so a hard short on the bus won't destroy it, though it will drag the rail — which loops back to the undervoltage point above.
Receiver thresholds leave real margin — if the bus is terminated. Differential thresholds are 0.5/0.9 V (max dominant threshold 0.9 V) with 120 mV typical hysteresis, against a guaranteed 1.5 V minimum dominant output into 60 Ω. Input resistance is ~15 kΩ per node (30 kΩ differential), so node count barely loads a terminated bus; the receiver thresholds are only specified for common-mode within ±30 V, so stay inside that. On the transmit side, dominant CANH must land at 2.75–4.5 V (typ 3.5 V) and CANL at 0.5–2.25 V (typ 1.5 V), with transmitter symmetry — VCC − VCANH − VCANL — within ±400 mV.
For 5 Mbit/s FD, the timing numbers to check are loop delay and bit-width symmetry. Worst-case TXD-to-RXD loop delay is 220 ns (40 min / 220 max on the base part; the datasheet gives no typical). At the 200 ns fast-phase bit time, the datasheet guarantees the transmitted recessive bit width lands in 155–210 ns and the RXD bit time in 120–220 ns, with receiver timing symmetry Δtrec of −45/+15 ns. Those are the bounds your bit-timing configuration has to absorb.
Thermals: the SO8 is the constraint, not the die. Rth(vj-a) is 155 K/W for the SO8 versus 55 K/W for the HVSON8, and all specs are guaranteed over Tvj = −40 to +150 °C. On the HVSON8, the die ground connects to both the GND pin and the exposed center pad — solder the pad down; leaving it floating is electrically tolerable but throws away the heat sinking you paid for.
Testing the TJA1051T on the bench
A bring-up sequence with datasheet-defined pass/fail bounds:
- Continuity/pinout check first. Confirm pin 5 is unconnected on the base part, and that your footprint matches the variant actually stuffed. This catches the most common silent killer before power is ever applied.
- VCC at the pin: 4.5–5.5 V. A reading inside the 3.5–4.5 V UV band is a fault, not "close enough" — the part is disengaged there.
- Supply-current sanity. TXD high (recessive): expect 5 mA typ / 10 max. TXD low (dominant): 50 mA typ / 70 max. These two readings confirm the drivers are alive and the rail is loaded correctly.
- Dominant levels into the real terminated bus. CANH 2.75–4.5 V, CANL 0.5–2.25 V, symmetry within ±400 mV. Out-of-window readings usually mean bad or missing termination, not a bad transceiver.
- Receive path. With a remote node driving dominant, RXD must read LOW at the MCU; recessive, HIGH. RXD is push-pull, so a hanging or weak RXD points at an external load problem.
- Loop-back timing. Inject a known TXD pattern and measure TXD→RXD loop delay (≤ 220 ns) and RXD bit width (120–220 ns at a 200 ns injected bit) on the scope.
- UV behavior. Ramp VCC down and confirm the bus pins go high-impedance rather than driving — this is specified behavior and worth verifying once, because it's your brownout defense.
- Corners. All DC specs are guaranteed over −40 to +150 °C junction; re-check dominant levels and UV behavior at your board's hot and cold ambients, not just room temperature.
Troubleshooting the TJA1051T
When a node "just doesn't work," work down this list — these five cover the overwhelming majority of bring-up faults:
- VCC sitting in the 3.5–4.5 V undervoltage band. The transceiver is switched off and invisible to the bus regardless of your logic. Measure at the pin, under load, during dominant transmission — a rail that reads fine at idle can droop into the trip window when the 50–70 mA dominant current hits.
- Missing or wrong 60 Ω termination. Every output spec assumes RL = 60 Ω; with no load you'll get invalid dominant levels and unreliable arbitration.
- S accidentally high. S has an internal pull-down, but a stray trace, a misconfigured GPIO, or a copy-pasted init from an /E design can hold S high — transmitter off, receive-only. You'll see the node listening fine but never transmitting.
- 3.3 V MCU on the base part. VIH ≥ 0.7·VCC means a 3.3 V high is not guaranteed over the full 4.5–5.5 V range — at VCC = 4.5 V the threshold is 3.15 V and a 3.3 V high clears it, but at 5.5 V it's 3.85 V and the same high can fall below it. The line can look fine on a scope while the part intermittently fails to recognize it. The fix is the /3 variant, not a level-shifting hack.
- Logic-pin damage. The TXD/RXD/S side is rated −0.3 to +7 V and ±4 kV ESD — half the bus pins' tolerance. A bench fault or hot-plug event on the logic side kills parts that the bus-side armor would have shrugged off.
Two behavioral quirks that look like failures but aren't: if the die exceeds Tj(sd), the output drivers disable and stay off until temperature drops and TXD returns recessive — so after a thermal event, release TXD high and let it cool before declaring the part dead. And if TXD is held dominant by a hung controller, the driver times out after tto(dom) (0.3–5 ms) and releases the bus — that's the protection working, and the fix is upstream at the controller. If you need to isolate a misbehaving node without removing it, force Silent mode (S = HIGH): the datasheet names exactly this use, preventing a faulty CAN controller from disrupting network communications.
Part page: TJA1051T.