PY32F002B: A Practical Bring-Up and Integration Guide for Hardware Engineers

The PY32F002B is an entry-level 32-bit Arm Cortex-M0+ microcontroller from Puya, running at up to 24 MHz with 24 KB of flash and 3 KB of SRAM, in compact packages (QFN20, TSSOP20, SOP16, SOP14, MSOP10). It integrates a 12-bit ADC, two internal comparators, multiple timers (advanced, general, and low-power), an independent watchdog (IWDG), USART, SPI, I²C, and SWD debug, all on a wide 1.7 V–5.5 V supply. That supply range is the headline: it runs directly off a Li-ion cell or a loose 3–5 V rail with no external LDO, making it a natural fit for battery-powered sensor nodes, low-cost embedded control, and motor/PWM control loops where you'd otherwise reach for an 8- or 16-bit part. The datasheet positions the M0+ core as an upgrade path from 8/16-bit MCUs — better code density, a unified 32-bit toolchain, ultra-low power operation — without adding cost or board area.

Before you lock in a part number: the datasheet's ordering-information section (Section 7) provides the decode diagram mapping orderable part-number suffixes to these physical packages — the suffix-to-package mapping isn't obvious from the package list alone, so consult it to select the correct footprint and variant.

Think of this post as a bench sign-off procedure: a sequence of checks to run as you integrate the part into a design, and a second set to run once the board is alive. Each check is tied to a specific datasheet value so you know exactly what "pass" looks like.

Check 1: Power Supply and Reset (What rails and reset thresholds do I need to design for?)

Start with the supply, because it drives everything else on the board.

• Working range is 1.7 V–5.5 V. This is a genuine design liberty: you can power the part directly from a Li-ion cell (3.7 V nominal), a LiFePO4 or alkaline stack, or an unregulated 3–5 V rail without an LDO. Keep the 1.7 V lower bound in mind — below that, power-on reset (POR) becomes the operative behavior.
• Absolute maximum on VCC is 6.25 V, and pin inputs must stay within VCC + 0.3 V / −0.3 V. Exceeding the absolute-maximum table can permanently damage the chip, and the datasheet explicitly warns that the table lists withstand levels only — it does not imply functional operation, and long-term operation at max conditions may affect reliability. Size your clamps and rail protection so VCC never exceeds 6.25 V and every GPIO input stays inside the VCC ± 0.3 V window.
• Use the 8-level brown-out reset (BOR) deliberately. The part has POR/PDR plus BOR with rising thresholds VBORR1–VBORR8 and matching falling thresholds VBORF1–VBORF8. The full threshold table (typical values, min/max in parentheses):

BOR hysteresis is 100 mV typ, and the POR/PDR thresholds sit below all BOR levels (rising 1.6 V typ, falling 1.55 V typ, 50 mV PDR hysteresis). The key takeaway: on battery designs with soft discharge curves, pick a BOR level above your minimum valid operating point so the MCU resets cleanly instead of hanging in a nondeterministic low-voltage state. One subtlety — if your design must genuinely run down at the 1.7 V floor, BOR level 000's falling threshold max (1.8 V) sits above your operating minimum, so you can't simultaneously guarantee operation at 1.7 V and have BOR trip with useful margin below it. In that case, disable BOR and rely on PDR alone.

Check 2: Surrounding Components (What goes around the chip?)

• Decoupling: the datasheet does not publish explicit decoupling capacitor values, so this is general practice, not a spec: 0.1 µF at the pins plus 1–10 µF of bulk capacitance is the usual approach.
• Pull-ups/pull-downs: GPIO pulls are field-programmable (pull-up, pull-down, or float) with a configuration lock function. Prefer the on-chip pulls; add external resistors only where bus speed demands a stronger pull on fast open-drain lines.
• SWD lines: at reset, PB6/SWDIO defaults to an internal pull-up and PA2/SWCLK defaults to an internal pull-down. Don't add external pulls that fight these defaults — it's a common source of confusing debug behavior.
• Transient protection on external lines: connector-facing I/O should get TVS/Schottky clamping to the rails to respect the VCC ± 0.3 V pin window. The part's own robustness ratings are respectable — ESD of 6 kV HBM / 1 kV CDM / 200 V MM, static latch-up trigger of 200 mA, and EFT immunity per IEC 61000-4-4 of 2 kV on I/O pins and 4 kV on power pins (both Class A). But 2 kV on I/O is a moderate burst level, so keep suppression at the connector rather than trusting the MCU pin alone.

Check 3: Clocking (Do I need a crystal?)

• No crystal needed for most designs. The CPU boots on the internal 24 MHz HSI by default. You also get a 32.768 kHz internal LSI, an optional external 4–32 MHz input clock, and an external 32.768 kHz LSE.
• Bus prescaling matters if you bring in a faster clock. AHB and APB are derived by dividers from the system clock and are capped at 24 MHz. If you feed in a 32 MHz external clock, the buses still top out at 24 MHz — plan your prescalers rather than assuming 1:1.
• Don't trust the LSI for accurate timekeeping. It's spec'd at 31.6–33.6 kHz (typ 32.6 kHz) at 25 °C, but drifts ±10 % over 0–85 °C and ±20 % over −40–85 °C. A 1000 ms timer built on LSI can be off by ±20 % at cold. Verify your IWDG timeout margin against this drift — a watchdog period computed from the nominal frequency will shrink at −40 °C.

Check 4: Analog Setup (How do I get good ADC and comparator readings?)

This is where the PY32F002B has part-specific quirks you won't find on a generic M0+:

• Two independent 1.5 V-class references, each with its own startup. The ADC's internal reference (VREF15 = 1.485–1.515 V at 25 °C / VCC = 3.3 V, temperature coefficient ≤ 120 ppm/°C over −40…85 °C) takes 10 µs typ / 15 µs max to start. The comparator's reference is a separate 4-bit DAC block with its own 10 µs typ / 15 µs max start time and ±0.5 LSB absolute variation. Budget the settle time separately for each before trusting a threshold or conversion after waking from Stop.
• Comparator thresholds need no external divider. The reference ladder offers 15 taps of VCC (1/16…15/16) plus the internal 1.5 V reference. Comparators can wake the chip from both Sleep and Stop via EXTI — ideal for event-driven battery sensors — and can drive a timer input to generate the OREF_CLR brake event for cycle-by-cycle PWM shutdown in motor or power-control loops.
• The on-die temperature sensor has strict timing rules. Model: average slope 2.3–2.7 mV/°C (typ 2.5), V30 = 0.74–0.78 V (typ 0.76 V) at 30 °C (±5 °C), linearity ±1 °C typ / ±2 °C max, start-up to continuous mode 70–120 µs, and ADC sampling time ≥ 9 µs when reading the temperature channel. Use the ≥ 9 µs sample time (not your normal one), single-point calibrate at ~30 °C with the published slope (T = (V − V30)/slope + 30), and wait out the startup before the first read.
• ADC reality check: conversion clock is up to 16 MHz at VCC ≥ 2.0 V (8 MHz at 1.7–2.0 V), with a 12-clock conversion and 3.5-clock minimum sample — roughly 1 MSPS at 300 µA. Linearity is INL ±3 LSB, DNL ±2 LSB (typ), so plan for ~10–11 effective bits, not a full 12. The internal sample-and-hold cap is 5 pF typ; with a short minimum sample window, keep source impedance low or lengthen the sample time. Up to 8 external + 2 internal channels, with reference selectable between the internal 1.5 V and VCC.

Check 5: Low-Power Strategy (How do I budget battery life?)

• Two power-saving modes: Sleep and Stop. There is no advertised Standby mode in the datasheet — don't design around a deepest-off mode that isn't documented.
• Stop-mode current depends on which regulator regime you're in: roughly 75.3 µA with the MR/LPR regulator on vs ~1.1–1.7 µA with it off — a 40× spread that hinges entirely on that configuration choice. Run-mode current is ~1.1 mA typ at 24 MHz HSI with flash on (~0.9 mA flash off), dropping to 160 µA → 108 µA at 32.768 kHz LSI depending on flash sleep.
• Wake sources from Stop are limited to five: GPIO, IWDG, nRST, COMP output, and LPTIM. High-speed clocks (PLL, HSI, HSE) are shut off in Stop, so a USART or SPI interrupt simply cannot wake it. Budget wake time too: 0.6 µs typ from Sleep, 6.4 µs typ from Stop (MR-powered) or 10.6 µs typ (LPR-powered), from flash with 24 MHz HSI.
• If you log data to flash, respect the endurance budget: 100,000 erase/write cycles across −40 to +85 °C, and 20-year data retention rated only at 10,000 cycles and 55 °C. At one page write per minute you'd exhaust 100k cycles in ~69 days; at one per hour, ~11 years. Use wear leveling across the 24 KB flash, and note that retention degrades if you simultaneously run hot and near the endurance ceiling. Page program is 1.0 ms typ / 1.5 ms max; page/sector/mass erase 3.5 ms typ / 5.0 ms max.

Known limitation: the datasheet does not publish decoupling-capacitor values, a GPIO weak-pull resistance, or an injection-current (IINJ) specification. Those surrounding-component decisions must come from general practice and your own validation, not the spec.

Post-Integration Verification (How do I test it?)

Before you test anything, note the datasheet's own warning on typical values: they're based on T_A = 25 °C and V_CC = 3.3 V and are for design guidance only, not tested. ADC accuracy is characterized as 95% of chips within the given number across temperature. Treat every "typ" figure below as a deviation flag, not a hard pass/fail line.

1. Rail check. Apply 1.7–5.5 V and scope for overshoot past the 6.25 V abs-max at power-up and undershoot below −0.3 V. Verify pin inputs stay within VCC ± 0.3 V under all conditions, including connector transients.
2. Current sanity. Measure run-mode IDD against ~1.1 mA at 24 MHz (flash on) — an early catch for clock or peripheral misconfiguration. Measure Stop current and determine which regulator regime you're in (75.3 µA vs 1.1–1.7 µA).
3. Brown-out sweep. Ramp the rail down through your chosen BOR level and confirm reset occurs near the falling threshold with ~100 mV of hysteresis — e.g. level 110 should reset falling from ~2.9 V, level 111 from ~3.1 V. Confirm a clean reset with no hang mid-droop.
4. Clock verification. Confirm the core boots at 24 MHz HSI. If you use the LSI, measure it and check your timebase margins against the ±10–20 % drift.
5. Analog settle checks. After each wake or reset, wait ≥ 15 µs (max) before the first ADC or comparator read. Verify the temperature sensor path uses ≥ 9 µs sample time and 70–120 µs startup, and cross-check readings against a known-good sensor.
6. Wake behavior. Confirm the comparator wakes the device from Sleep and Stop via EXTI using the on-chip threshold ladder.
7. ESD/EFT qualification. Design test coupons to the published withstand levels: 6 kV HBM, 1 kV CDM, 200 V MM, 200 mA latch-up, 2 kV I/O and 4 kV power EFT. A board failing below 6 kV HBM at connector-facing pins means your clamps are inadequate.
8. Peripheral and memory checkout. Enable each block one at a time and watch the current delta — advanced TIM1, general and low-power timers, SysTick, IWDG, SPI, I²C, USART, and two comparators are all on this part. Run a stack/free-RAM check against the 3 KB SRAM budget.
9. SWD recoverability. After configuring GPIOs (including the config lock), verify you can still reconnect SWD and re-flash. Do this before production, on every firmware that touches pin configuration.
10. Thermal check. The explicit operating range is T_A = −40 to +85 °C with T_J = −40 to +90 °C. At +85 °C ambient you have only 5 °C of junction headroom; with sub-1.1 mA run currents self-heating is negligible, but don't stack full-speed operation in a hot enclosure without margin.

Troubleshooting (What do I check when it misbehaves?)

• Random resets in a loop: read the reset-status flags first — the reset module triggers on POR/PDR, BOR, NRST, IWDG, software reset (SYSRESETREQ), and option-byte loading, and each needs a different fix. If it's brown-out, a rail drooping more than 100 mV through the ~2.9–3.1 V band with BOR level 110 set is exactly the intermittent-reset symptom; raise the rail margin or adjust the BOR level so droop stays above the falling threshold plus hysteresis.
• Won't wake from Stop: check that your wake source is one of the five allowed — GPIO, IWDG, nRST, COMP output, or LPTIM. Trying to wake on a USART or SPI interrupt can't work because those clocks are off in Stop. Switch to a comparator, GPIO, or LPTIM wake.
• Timing off after wake: you likely misapplied the wake-time budget. Sleep wake is 0.6 µs typ; Stop wake is 6.4 or 10.6 µs typ — and the internal-reference settle (10 µs typ / 15 µs max) is on top of that, not included in it. Budget both without double-counting.
• Intermittent watchdog resets: the IWDG runs from the LSI, which drifts up to ±20 % over the full cold range. Don't set the timeout tight against the nominal computed value — leave at least 20 % margin.
• Dead or unresponsive after flashing: check whether you locked or remapped the SWD pins. PB6/SWDIO and PA2/SWCLK have specific default pull states at reset, and the GPIO config lock will block a debugger connection you expect. Use nRST to regain control — it's also a Stop wake source.
• Analog first-reads look wrong: you're almost certainly violating the reference settle (≥ 15 µs max) or temperature-sensor sample-time (≥ 9 µs) constraints. Fix the timing, not the filtering.

⚠ Not production tested: several specification tables — GPIO port characteristics, ADC values, POR/BOR rows, flash endurance — are explicitly labeled as based on core verification or assessment, not production tested. In the datasheet itself, this caveat appears only as small-print footnote paragraphs beneath each table's rows (referenced by superscript markers), not as a visually distinct callout — so it's easy to miss. That doesn't make the values wrong, but it means your own bench measurements are the real qualification. Leave margin wherever a typical value is load-bearing.

Part page: PY32F002B.