The most common misconception about the PCA9517D is that it's a symmetric buffer — that a LOW on one side looks like a LOW on the other. It isn't, and treating it as symmetric is how designs end up with arbitration and clock stretching that silently fail. The B-side (2.7–5.5 V) carries a deliberate ~0.5 V static offset, while the A-side drives a hard LOW near 0 V. That asymmetry is not a quirk; it's the mechanism that makes the part lock-up-free, and it drives nearly every design decision below.
The PCA9517D is a two-channel (SDA + SCL), bidirectional I²C-bus/SMBus repeater that level-translates between a low-voltage side (down to 0.9 V) and a higher-voltage side (2.7–5.5 V). Its job is to join two halves of an I²C bus while isolating them for both voltage and capacitance — each half supports up to 400 pF, so two 400 pF buses can be connected through one part. Typical uses: interfacing a 0.9–1.2 V sensor or MCU to a 3.3 V or 5 V bus, splitting a long/high-capacitance bus into two legal halves, and isolating a hot-pluggable or powered-down segment (all I/Os go high-impedance when unpowered and are overvoltage-tolerant to 5.5 V). The datasheet's reference application is a 3.3 V master bus to a 1.2 V slave bus, both at 400 kHz, with masters allowed on either side.
Wiring the PCA9517D (How do I integrate the PCA9517D into a design?)
The two sides are deliberately asymmetric — wire them accordingly:
- B-side (V_CCB, 2.7–5.5 V) drivers behave like the PCA9515A and carry a ~0.5 V static offset: the internal pull-down LOW is set to ~0.5 V, with the input threshold set ~70 mV lower (~0.43 V). This offset is what prevents self-lock-up.
- A-side (V_CCA, 0.9–5.5 V) drives a hard LOW (~0 V) to suit the small voltage swings of low-voltage logic, with its input threshold at 0.3·V_CCA.
- Translation behavior: an A-side LOW below 0.3·V_CCA turns the B-side driver on down to ~0.5 V; when A rises above 0.3·V_CCA the B pull-down releases and the external pull-up raises the pin. When B falls below 0.3·V_CCA, the A-side pulls to 0 V. So a B-side LOW becomes a nearly 0 V LOW on the A side — the LOW levels are not the same on both sides.
Pinout for the SO8 package (PCA9517D, SOT96-1, 3.9 mm body): pin 1 VCCA, 2 SCLA, 3 SDAA, 4 GND, 5 EN, 6 SDAB, 7 SCLB, 8 VCCB. The PCA9517DP is the TSSOP8 (SOT505-1, 3 mm body) variant with the same function.
Topology rules, straight from the datasheet:
- Each side must have its own pull-up resistors. The part is open-drain on both sides; a missing pull-up on either side leaves the line undefined.
- Never connect a rise-time-accelerator buffer to the B-side. The B-side's static-offset design forbids it — named examples include PCA9510/9511/9512/9513/9514, PCA9515A, PCA9516A, the PCA9517 B-side, and PCA9518.
- A-sides can be tied together for a sanctioned star topology, and the A-side can connect to any buffer, static or dynamic offset. The reference star example uses 10 kΩ pull-ups per segment.
- Series connection A-side→B-side is allowed with no offset build-up — only time-of-flight delays accumulate. The datasheet sets no fixed stage count; the limit is your delay budget versus bus speed (see the testing section).
Power and enable are forgiving:
- A built-in power-up circuit holds the output drivers off until V_CCB > 2.5 V and V_CCA > 0.8 V, and the two supplies may be applied in any order. No sequencing hardware needed.
- EN must be HIGH after power-up for the buffers to operate. EN thresholds are referenced to V_CCB: V_IL ≤ 0.3·V_CCB, V_IH ≥ 0.7·V_CCB. Tie or pull EN deliberately — don't leave it floating.
- All I/Os and EN are overvoltage-tolerant to 5.5 V even when unpowered, and SDA/SCL are high-impedance when the device is off — useful for tying a powered bus onto a card that may be down.
For the datasheet's short-cable/board-to-board reference application, copy its concrete values: 75 Ω terminations on the differential pair, pull-ups on the input side, and 10 kΩ pull-downs on the output side. Use it as a template for short-cable links, not long point-to-point traces.
Design rules for the PCA9517D (What do I need to watch out for?)
The 0.4 V rule is the single most important constraint. For the repeater to recognize and forward a LOW that a B-side slave pulls — which is exactly what happens during arbitration and clock stretching — the LOW at the B-side input must reach ≤ 0.4 V. The B-side internal driver's own pull-down LOW sits at only ~0.5 V, with its input threshold set about 70 mV lower at ~0.43 V, so the device deliberately does not recognize its own LOW. An external device must pull below 0.4 V to be heard. If your B-side pull-up/slave combination can't sink the bus to 0.4 V, stretched and arbitrated lows get lost — silently, with no error indication.
Threshold asymmetry extends to first-vs-subsequent LOWs. The B-side specifies V_IL for the first LOW on SDAB/SCLB and V_ILc for the second and subsequent LOWs — two different thresholds. On the A-side, with envelope noise the input must go below 0.3·V_CCA for stable performance. Don't design around a single threshold value.
Timing budget at Fast mode. Propagation delays are direction-dependent (Table 5 max values):
| Parameter | Max |
|---|---|
| B→A t_PLH | 250 ns |
| B→A t_PHL (V_CCA ≥ 3 V) | 300 ns |
| A→B t_PLH | 110 ns |
| A→B t_PHL | 230 ns |
| B-side rise t_t(LH) | 170 ns |
| A-side rise t_t(LH) | 30 ns |
The B-side rise time (up to 170 ns) is the slowest edge the part produces and dominates the rise-time budget at 400 kHz. For series chains, the worst-case per-stage delay is the B→A path, up to 300 ns; as a working estimate, holding total per-hop delay to about a third of the bit period gives roughly 2–3 stages at 400 kHz and up to ~11 at 100 kHz — that margin fraction is engineering practice, not a datasheet spec, so verify on your scope.
EN has a level and a timing constraint. EN must be HIGH at least 100 ns before START and held at least 100 ns after STOP, and it should only change state when the global bus and the repeater port are idle — never mid-transaction. EN also draws a small but real input current (IIL(EN) typ −10 µA, max −30 µA at V_I = 0.2 V, V_CC = 3.6 V).
Absolute limits. DC current on any pin: max 50 mA. Total power dissipation: max 100 mW. Ambient −40…+85 °C, junction max 125 °C, abs-max voltages −0.5 to +7 V on the supplies and B-side bus/EN. Standard-mode devices only guarantee 3 mA drive, which limits termination current to 3 mA in a generic multi-master system.
Known limitation: the datasheet specifies no decoupling capacitor value, no external ESD/clamp components, and no pull-up resistor formulas. The 5.5 V overvoltage tolerance is a hot-plug margin, not an IEC-ESD rating — external clamp protection for harsh cable environments is general practice, not a documented spec here.
Testing the PCA9517D (How do I verify my PCA9517D circuit works?)
Electrical specs are defined over V_CC = 2.7–5.5 V, GND = 0 V, T_amb = −40 to +85 °C. One structural fact to keep in mind: all logic and I/Os are powered from V_CCB; V_CCA only supplies the 0.3·V_CCA reference to the A-side input comparators and the power-good detector. The A rail's pull-up level, not the chip logic, sets the A-side HIGH level.
- Power-up: apply V_CCB within 2.7–5.5 V and V_CCA within its adjustable range; confirm drivers stay off until V_CCB > 2.5 V and V_CCA > 0.8 V, then go active only after EN is HIGH.
- Functional translation: drive a LOW on each side. An A-side LOW below 0.3·V_CCA must turn the B-side driver on (~0.5 V, then released to the pull-up); a B-side LOW must pull the A-side to ~0 V (0.1 V typ / 0.2 V max at 6 mA).
- Arbitration/clock-stretch check: trigger a real arbitration or clock-stretching event (two masters, or a stretch-capable slave) while probing the B-side input. Set a scope threshold at 0.4 V and verify B-side SDA/SCL dips below it during the event — anything above 0.4 V means the event is silently lost.
- Timing: measure against Table 5 using the datasheet's waveform references — output measured at 50%·V_CCA if V_CCA < 2 V, or at 1.5 V if V_CCA > 2 V, with a 0.5 V input threshold on the rising input edge. Watch the B-side rise (max 170 ns) at your pull-up value and bus capacitance, and confirm EN setup/hold of ≥100 ns around START/STOP.
- Full-bus run: operate at your target rate (e.g. 400 kHz) with real slaves on both sides, confirm ACK levels, and toggle EN only while idle.
- Margin sanity: verify bus LOW current keeps every pin under 50 mA DC and total dissipation under 100 mW across temperature.
Troubleshooting (Why is my PCA9517D circuit misbehaving?)
- Bus stuck / no communication at all: check both rails against the trip points (drivers off until V_CCB > 2.5 V and V_CCA > 0.8 V; below 2.7 V on B you're outside the rated supply). Then check EN — it must be HIGH, with V_IH ≥ 0.7·V_CCB; a floating or half-driven EN leaves the buffer off. Finally, confirm pull-ups exist on both sides.
- Arbitration or clock stretching silently fails: the classic trap. The B-side input LOW must reach ≤ 0.4 V to be recognized and forwarded. Tighten the B-side sink strength or reduce the pull-up value until stretched/arbitrated lows cross 0.4 V.
- Multi-master design locks up: check the topology. Rise-time-accelerator buffers (PCA9510/11/12/13/14, PCA9515A, PCA9516A, PCA9518) must never hang on the B-side — connect them only on the A-side, which may tie to any static or dynamic-offset buffer. Build stars from tied-together A-sides and daisy-chain only A→B.
- A B-side line appears stuck around 0.5 V: that's the device's own internal pull-down, deliberately held above its ~0.43 V input threshold so it doesn't see itself. It's not a real LOW — an external driver must pull further down for anything to happen.
- Weak or timing-marginal signals at Fast mode: the B-side rise (t_t(LH) up to 170 ns) is the slowest edge; reduce B-side pull-up resistance or bus capacitance and re-measure. Budget the direction-dependent delays: B→A t_PLH max 250 ns, A→B t_PLH max 110 ns.
- Part runs warm: check per-pin DC current (≤50 mA) and total dissipation (≤100 mW) under worst-case bus loading, remembering Standard-mode masters only guarantee 3 mA sink.
- Suspected damaged or hot-plugged segment: I/Os are 5.5 V-tolerant even unpowered, so a powered or unpowered disconnected segment shouldn't back-feed the bus — if it does, the fault is elsewhere in the path.
One last note on supply current: there's no deep-sleep mode. Idle-HIGH supply current (ICCH) is 1.5 mA typ / 5 mA max, quiescent current in contention (ICCAc) is the same 1.5 mA typ / 5 mA max, and the V_CCA pin draws at most 1 mA — so the chip's own draw is essentially flat between idle and active. Budget ~5 mA max for the part plus whatever your external pull-ups sink.
Part page: PCA9517D.