MCP2518FD registers - register map, bit fields and reset values

September 12, 2026 · AI-generated from the datasheet, fact-checked by two independent LLM critics

The MCP2518FD is a CAN FD controller with a 4-wire SPI interface (modes 0,0 and 1,1). Its register map is a flat 12-bit address space (0x000-0xFFF) with no bank switching, split into three regions: CAN FD controller SFRs (~752 bytes, 0x000-0x1FF region), a 2 Kbyte Message RAM for TX/RX/TEF message objects, and a 24-byte MCP2518FD-specific SFR block at 0xE00-0xE17. All SFRs are 32-bit wide; the LSB sits at the lower byte address (e.g. the LSB of CiCON is at 0x000).

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MCP2518FD-specific SFR block: OSC (0xE00), IOCON (0xE04), CRC (0xE08), ECCCON (0xE0C), ECCSTAT (0xE10), DEVID (0xE14)

Chip-level registers not tied to the CAN core (Table 3-1):

Address	Register	Purpose
0xE00-E03	OSC	Oscillator/PLL/clk-out control: PLLEN, OSCDIS, SCLKDIV, CLKODIV, LPMEN, PLL/OSC/SCLK ready
0xE04-E07	IOCON	I/O config: GPIO[1:0], LAT, TRIS, INTOD, SOF, TXCANOD, XSTBYEN, power mode
0xE08-E0B	CRC	SPI CRC register + CRC/FERR interrupt-enable & flags
0xE0C-E0F	ECCCON	RAM ECC control: ECCEN, parity, SECIE/DEDIE
0xE10-E13	ECCSTAT	ECC status: SECIF/DEDIF, error address ERRADDR
0xE14-E17	DEVID	Device ID + silicon revision

OSC bit fields

Bit	Field	Meaning
0	PLLEN	PLL enable: 1 = system clock from 10x PLL; 0 = direct from XTAL. (Config mode only)
1	-	unimplemented
2	OSCDIS	Oscillator disable / sleep: 1 = clock disabled, device in Sleep; 0 = clock enabled. Clearing it while in Sleep wakes the part back to Configuration mode.
3	LPMEN	Low Power Mode enable: 1 = in Sleep the clock stops + most of chip powers down, register & RAM values lost, wakes on nCS or RXCAN; 0 = in Sleep the clock stops but register & RAM retained, wakes on clearing OSCDIS or RXCAN.
4	SCLKDIV	System clock divider: 1 = SCLK /2; 0 = /1.
6-5	CLKODIV[1:0]	CLKO output divisor: 00=/1, 01=/2, 10=/4, 11=/10.
8	PLLRDY	Status: 1 = PLL locked.
10	OSCRDY	Status: 1 = clock running & stable.
12	SCLKRDY	Status: reflects SCLKDIV setting.

OSC bits 1, 7, 9, 11 and 13+ are reserved. LPMEN does not put the device into LPM itself - it selects which sleep mode is entered after you request Sleep via CiCON.REQOP; to wake on RXCAN, CiINT.WAKIE must be set.

IOCON bit fields

Bit	Field	Meaning
6	XSTBYEN	Transceiver-standby pin control enable: 1 = XSTBY controlled automatically; 0 = disabled.
9-8	LAT1/LAT0	GPIO latches (drive high/low).
1-0	TRIS1/TRIS0	GPIO direction: 1 = input, 0 = output.

IOCON also configures CLKO/SOF and TXCANOD (push-pull vs open-drain, for controller-to-controller networks without a transceiver). IOCON bits 31-8 are reserved. The IOCON bit fields must be written using single data-byte SFR WRITE instructions (no 4-byte burst).

ECCCON bit fields

Bit	Field	Meaning
0	ECCEN	ECC enable: 1 = RAM ECC enabled; 0 = disabled.
1	SECIE	Single-error-correct interrupt enable.
2	DEDIE	Double-error-detect interrupt enable.
14-8	PARITY[6:0]	Parity bits used on RAM writes when ECC is disabled.

ECCSTAT bit fields

Bit	Field	Meaning
-	SECIF	Single-error-correct interrupt flag
-	DEDIF	Double-error-detect interrupt flag
-	ERRADDR	ECC error address

ECCSTAT bits 31-28, 15-3 and 0 are reserved.

DEVID bit fields

Bit	Field	Meaning
7-4	ID[3:0]	Device ID
3-0	REV[3:0]	Silicon Revision

DEVID is read-only and hard-wired; writes have no effect. The datasheet defines only the field layout - it does not state the expected numeric ID/REV read-back value, so pin your sanity-check constant from Microchip's silicon revision table, not from this page.

CAN module control and bit timing: CiCON (0x000), CiNBTCFG (0x004), CiDBTCFG (0x008), CiTDC (0x00C), CiTBC (0x010), CiTSCON (0x014)

CiCON - CAN module control (0x000)

Bit	Field	Meaning
26-24	REQOP[2:0]	Requested operation mode: 000 Normal CAN FD; 001 Sleep; 010 Internal Loopback; 011 Listen Only; 100 Configuration; 101 External Loopback; 110 Normal CAN 2.0; 111 Restricted Operation.
23-21	OPMOD[2:0]	Operation-mode status - same code as REQOP, showing the mode the module has actually entered. In Sleep it reads 100 (Configuration) and OSC.OSCDIS reads 1, used as the wake handshake.
20	TXQEN	Transmit-Queue enable: 1 = reserves TXQ space in RAM.
19	STEF	Store in Transmit Event FIFO: 1 = saves transmitted messages to TEF and reserves RAM.
18	SERR2LOM	On system error: 1 = go to Listen Only; 0 = go to Restricted Operation.
17	ESIGM	ESI in gateway mode.
16	RTXAT	Restrict retransmission attempts.
12	BRSDIS	Disable bit-rate switching.
8	WAKFIL	CAN bus line wake-up filter enable: 1 = use bus-line filter for wake-up.

REQOP/OPMOD, TXQEN, STEF, SERR2LOM, ESIGM, RTXAT, BRSDIS, WAKFIL, TXBWS and ABAT can only be modified in Configuration mode. ABAT is cleared by the module itself once all transmissions are aborted - do not overwrite it mid-abort.

CiNBTCFG - Nominal bit-time config (0x004)

Bits	Field	Meaning
31-24	BRP[7:0]	Baud-rate prescaler: 0 -> TQ = 1/Fsys ... 255 -> TQ = 256/Fsys
20-16	TSEG1	Time segment 1 (Propagation + Phase 1): 1...32 x TQ
11-8	TSEG2	Time segment 2 (Phase 2): 1...16 x TQ
3-0	SJW	Synchronization jump width: 1...16 x TQ

The register pages also show the wider field interpretation (TSEG1 up to 256 TQ, TSEG2/SJW up to 128 TQ). Configuration-mode-only writes.

CiDBTCFG - Data-phase bit-time config (0x008)

Same BRP/TSEG1/TSEG2/SJW structure but for the data/bit-rate-switching phase. Holds the smaller TQ ranges (TSEG1 up to 32 TQ, TSEG2/SJW up to 16 TQ).

CiTDC - Transmitter delay compensation (0x00C)

Bits	Field	Meaning
17-16	TDCMOD[1:0]	TDC mode / SSP: 00 disabled; 01 manual (use TDCV+TDCO); 10/11 auto (measure delay, add TDCO)
14-8	TDCO[6:0]	TDC offset, two's complement (-64...+63 x TSYSCLK)
5-0	TDCV[5:0]	Measured delay value (0...63 x TSYSCLK)
25	EDGFLTEN	Edge filtering during bus-integration state (ISO 11898-1:2015)
24	SID11EN	12-bit SID in CAN FD base-format messages

CiTSCON - Timestamp config (0x014) and CiTBC (0x010)

Bits	Field	Meaning
16	TBCEN	Time-base-counter enable
9-0	TBCPRE[9:0]	TBC prescaler: 0 -> +1/clock ... 1023 -> +1/1024 clocks
17	TSEOF	Stamp at frame-valid (end-of-frame) vs start-of-frame
18	TSRES	FD-frame resolution point

CiTBC[31:0] is the free-running time-base counter value (stops/resets when TBCEN=0).

Interrupts, error counters and diagnostics: CiVEC (0x018), CiINT (0x01C), CiRXIF (0x020), CiTXIF (0x024), CiTREC (0x034), CiBDIAG0 (0x038), CiBDIAG1 (0x03C)

Register	Addr	Role
CiVEC	0x018	Interrupt code: read-only ICODE[6:0] gives the highest-priority pending interrupt (e.g. 1000001 = error, 1000010 = wake, 1001000 = invalid message, per-FIFO codes 0000001...0011111, 0000000 = TXQ). Flags set by hardware, cleared by the application.
CiINT	0x01C	Interrupt enable/flag bits: IVM, WAK, CERR, SERR, RXOV, TXAT, SPI-CRC, ECC, TEF, MOD, TBC, RX, TX
CiRXIF	0x020	Receive interrupt status, one bit per FIFO (RFOVIF/RFIF), write-1-to-clear
CiTXIF	0x024	Transmit interrupt status, one bit per FIFO, write-1-to-clear
CiRXOVIF	0x028	Receive-overflow interrupt status, write-1-to-clear
CiTXATIF	0x02C	Transmit-abort interrupt status, write-1-to-clear
CiTXREQ	0x030	Transmit-request status, one bit per FIFO
CiTREC	0x034	Error counters: TEC[7:0] + REC[7:0] (bits 15-0), plus TXBO, TXBP, RXBP, TXWARN, RXWARN, EWARN state bits
CiBDIAG0	0x038	Bus-diagnostic counters
CiBDIAG1	0x03C	Bus-diagnostic counters

Transmit event FIFO and TX queue: CiTEFCON (0x040), CiTEFSTA (0x044), CiTEFUA (0x048), CiTXQCON (0x050), CiTXQSTA (0x054), CiTXQUA (0x058)

Register	Addr	Role
CiTEFCON	0x040	Transmit-event FIFO config (PLSIZE, FSIZE, TEFTSEN). Bit 23 reserved. Config-mode-only writes.
CiTEFSTA	0x044	Transmit-event FIFO status flags
CiTEFUA	0x048	User address: address of the next TEF message object
CiTXQCON	0x050	Transmit queue config
CiTXQSTA	0x054	Transmit queue status flags
CiTXQUA	0x058	User address: address of the next TXQ message object

Message FIFOs: CiFIFOCON1 (0x05C), CiFIFOSTA1 (0x060), CiFIFOUA1 (0x064), ... CiFIFOCON31 (0x1C4), CiFIFOSTA31 (0x1C8), CiFIFOUA31 (0x1CC)

31 FIFOs, each a 12-byte block (CON/STA/UA at +0/+4/+8), stride +0x00C: CiFIFOCONm = 0x05C + 0xC(m-1).

Register	Addr	Role
CiFIFOCON1	0x05C	FIFO 1 config: size/type/payload (TXEN, RXTSEN, PLSIZE, FSIZE, FRESET, TXREQ). Bits 15-11 and 23 reserved.
CiFIFOSTA1	0x060	FIFO 1 status: TXREQ, TXIF, TFULLIF, TNOTEMPTYIF, RXIF, etc.
CiFIFOUA1	0x064	FIFO 1 user address: address of the next message write/read
CiFIFOCON31	0x1C4	FIFO 31 config (stride-derived; CiFLTCON0 = 0x1D0 boundary confirms)
CiFIFOSTA31	0x1C8	FIFO 31 status
CiFIFOUA31	0x1CC	FIFO 31 user address

Traps: CiFIFOCONm.FRESET - wait until this bit is clear before taking any action (set in Config, auto-cleared in Normal mode). CiFIFOCONm.TXREQ - on a TX FIFO, clearing the bit to '0' while set ('1') will request a message abort. CiFIFOUA is not guaranteed to read correctly in Configuration mode.

Filters and masks: CiFLTCON0 (0x1D0), CiFLTOBJ0 (0x1F0), CiMASK0 (0x1F4), ... (CiFLTCONm with m = 0...7; CiFLTOBJm/CiMASKm with m = 0...31)

Stride-derived addresses: CiFLTCONm = 0x1D0 + 4m, CiFLTOBJm = 0x1F0 + 8m, CiMASKm = 0x1F4 + 8m.

CiFLTCONm - Filter control (m = 0...7)

Bits	Field	Meaning
7	FLTEN	Enable/disable each filter. Filters may only be modified while disabled.
4-0	F0BP	Pointer to the FIFO where a matching message is stored (0 = reserved TX Queue, cannot receive).
12-8	F1BP	Second filter-to-FIFO pointer.

CiFLTOBJm - Filter object (m = 0...31)

Bits	Field	Meaning
30	EXIDE	Match only extended (1) or standard (0) identifiers (when MIDE=1)
29	SID11	Standard-ID filter bit
28-11	EID[17:0]	Extended-ID filter bits
10-0	SID[10:0]	Standard-ID filter bits

CiMASKm - Mask register (m = 0...31)

Bits	Field	Meaning
30	MIDE	Match mode: only matching message type (1) vs both std/ext (0)
29	MSID11	Std-ID mask
28-11	MEID[17:0]	Extended-ID mask
10-0	MSID[10:0]	Std-ID mask

Message RAM object layouts (TXOBJ, RXOBJ, TEFOBJ)

The 2 Kbyte Message RAM holds the actual message objects. Allocation order: TEF objects first (only if CiCON.STEF = 1), then TXQ objects (only if CiCON.TXQEN = 1), then FIFO1 through FIFO31. The partition is configuration-dependent - do not compute addresses by hand; use the User Address fields (CiTEFUA, CiTXQUA, CiFIFOUAm).

TXOBJ (Table 3-5):

Word	Content
T0	SID / EID / SID11 (identifier)
T1	SEQ[22:0], FDF, BRS, RTR, IDE, DLC[3:0]
T2	Data bytes 3-0
T3	Data bytes 7-4
Ti	Data bytes n...n-3 (up to 64 B payload)

RXOBJ (Table 3-6):

Word	Content
R0	SID / EID / SID11 (identifier)
R1	FILHIT[4:0], reserved, ESI, FDF, BRS, RTR, IDE, DLC[3:0]
R2	RXMSGTS[31:0] - only present when CiFIFOCONm.RXTSEN = 1
R3	Data bytes 3-0
R4	Data bytes 7-4
Ri	Data bytes n...n-3

TEFOBJ (Table 3-7):

Word	Content
TE0	SID / EID / SID11
TE1	SEQ[22:0], ESI, FDF, BRS, RTR, IDE, DLC[3:0]
TE2	TXMSGTS[31:0] - only when CiTEFCON.TEFTSEN = 1

A max-size 64-byte RXOBJ is 18 words (72 B) without timestamp, 19 words (76 B) with timestamp.

SPI access and CRC

Every transaction is: nCS low -> Command C<3:0> -> Address A<11:0> -> data -> nCS high. Verified command formats:

RESET: C = 0b0000, A = 0x000. Only to be issued after the device has entered Configuration mode. Resets all SFRs and state machines like a POR and returns the device to Configuration mode; Message RAM is not changed. The reset occurs at the end of the instruction, when nCS goes high.
SFR WRITE SAFE (with CRC): 0b1100, A<11:0>, DB[A], CRC<15:8>, CRC<7:0>
SFR WRITE CRC: 0b1011, A<11:0>, N<7:0>, DB[A]...DB[A+n-1], CRC<15:8>, CRC<7:0>
Message-memory WRITE CRC / WRITE SAFE: 0b1011 / 0b1100 with A<11:0>, N<7:0> word count, then data words + CRC

SPI CRC: polynomial 0x8005 (CRC-16/USB), seed reset to 0xFFFF on every nCS assertion. The CRC runs over the address + data fields, not the command opcode. WRITE_CRC (0b1010) commits data before the CRC is checked (a mismatch sets CRC.CRCERRIF but the data is already written); WRITE_SAFE (0b1100) commits the 4-byte word only after a matching CRC.

SPI timing (Table 7-6): FSCK max 17 MHz (see note 3), TSCK min 59 ns, TSCKH/TSCKL min 20 ns, SDI setup/hold min 5 ns, SDO valid max 20 ns after SCK. Note 3 requires FSCK <= 0.85 x FSYSCLK/2 - at the maximum 40 MHz SYSCLK this yields exactly 17 MHz. SYSCLK is 40 or 20 MHz (from a 40/20/4 MHz crystal or external clock; the 4 MHz input can be PLL-multiplied x10 to 40 MHz). At 20 MHz SYSCLK the FSCK cap is 8.5 MHz; with SCLKDIV = /2 it drops to 4.25 MHz; a 4 MHz crystal without PLL gives 1.7 MHz. Do not leave SDO floating while asleep - enable a pull/pull-down on the MCU pin connected to SDO.

Troubleshooting

Config-only writes ignored: REQOP/OPMOD, TXQEN, STEF, SERR2LOM, ESIGM, RTXAT, BRSDIS, WAKFIL, TXBWS, ABAT in CiCON; PLLEN and SCLKDIV in OSC; TXEN/RXTSEN/PLSIZE/FSIZE in CiFIFOCONm and CiTEFCON are all Configuration-mode-only. Request Configuration via CiCON.REQOP = 100, then poll OPMOD until it reads 100 before writing.
Sleep handshake looks wrong: in Sleep, OPMOD reads 100 (Configuration) and OSC.OSCDIS reads 1 - this is by design. Poll OSCDIS to confirm the actual Sleep state.
Lost configuration after wake: OSC.LPMEN = 1 selects Low Power Mode where register and RAM values are lost on entry. If you need retention, use LPMEN = 0.
Unintended aborts: clearing CiFIFOCONm.TXREQ to 0 while set requests a message abort.
DEVID sanity check: read DEVID at 0xE14 after a SPI RESET; the value is hard-wired and identical before and after reset. The datasheet does not state the expected numeric ID/REV code - source it from Microchip's silicon revision table.
CRC mismatch behavior: with WRITE_CRC the data is committed before the check; use WRITE_SAFE when the CRC must actually protect the write.
FIFO addresses: CiFIFOUA reads are not guaranteed correct in Configuration mode; read them only outside Config, and never compute RAM object addresses by hand - follow CiTEFUA/CiTXQUA/CiFIFOUAm.

Part page: MCP2518FD.