The ICM-42607-C is a 6-axis MotionTracking IMU (accelerometer + gyroscope) from TDK InvenSense in a 2.5 × 3 × 0.91 mm, 14-pin LGA package, built for wearables and hearables — the datasheet names activity recognition, fitness/exercise classification, swimming, and head posture tracking as its intended software use cases. It runs six power modes down to 3.5 µA in sleep, includes on-chip motion functions (pedometer, tilt, wake-on-motion, and more) so a host MCU doesn't have to compute them, and talks over I3C, I²C, or SPI.
This guide is framed as the questions you'd actually ask before and during bring-up.
What is the ICM-42607-C?
Key facts beyond the summary above:
- Six power modes (Sleep, Standby, Accel Low-Power, Accel Low-Noise, Gyro Low-Noise, 6-Axis Low-Noise) via
GYRO_MODE/ACCEL_MODEinPWR_MGMT0. - Typical currents: Sleep 3.5 µA @ 25 °C, accel low-noise 0.2 mA, gyro low-noise 0.42 mA, 6-axis low-noise 0.55 mA.
- On-chip APEX motion functions: pedometer, tilt, low-g, freefall, wake-on-motion, significant motion detection.
- 2.25 Kbyte FIFO (see the SRAM-sharing caveat below), plus a readable die temperature sensor.
- Host interfaces: 12.5 MHz I3C, 1 MHz I²C, or 24 MHz SPI.
How do I wire it up?
Power: Both VDD and VDDIO run 1.71–3.6 V (typ 1.8 V); operating range −40 to +85 °C. Match VDDIO to your host I/O level.
Decoupling — use the datasheet BOM (Table 10) values, exactly:
| Ref | Cap | Dielectric / tol | Net |
|---|---|---|---|
| C1 | 0.1 µF | X7R ±10% | VDD |
| C2 | 2.2 µF | X7R ±10% | VDD |
| C3 | 10 nF | X7R ±10% | VDDIO |
So two bypass caps on VDD (0.1 µF + 2.2 µF), one 10 nF on VDDIO.
Pins to tie:
AP_CS→ VDDIO when using I²C/I³C.FSYNC→ GND if frame-sync isn't used.RESVpins (2, 3, 10, 11) → NC, GND, or VDDIO (any is acceptable per the datasheet).AP_AD0sets the I²C address LSB:b110100X, so you can hang two of these on one bus (0x68/0x69 equivalents).
I²C specifics: SDA/SCL are open-drain and need pull-ups to VDDIO. Hard limits: max bus speed 1 MHz (Fast-mode Plus), max capacitive load 550 pF per line. The datasheet doesn't publish a pull-up resistance value — size it against FM+ rise time and your actual trace capacitance.
Interrupts: INT1/INT2 can each be push-pull or open-drain. Open-drain needs an external pull-up to VDDIO; push-pull doesn't.
What should I watch out for?
1. Only the accelerometer has a Low-Power mode. The gyro is Low-Noise only. For always-on sensing, run the accel in Low-Power (duty-cycled) with the gyro off, and leave ACCEL_LP_CLK_SEL=0 (Wake-Up oscillator) — the datasheet's recommended lowest-power setting. Note: the datasheet publishes no LP-mode current figure, so budget by measurement. Also, in this mode you must clear RCOSC_REQ_ON_FIFO_THS_DIS (bit 0 of FIFO_CONFIG6) to 0 — leaving it at 1 lets the host receive invalid FIFO packets after a watermark trigger. Conversely, restore it to 1 before entering sleep modes, which avoids having to do a FIFO access/flush before entering sleep.
2. Forbidden LP ODR/averaging combos. In Low-Power mode there are combinations you must avoid — e.g. ODR 1600/800 Hz with any averaging, 400 Hz with 16×/32×/64×, 200 Hz with 64×.
3. Mode-transition timing. Gyro must be kept on for a minimum of 45 ms. After an off→on transition of either gyro or accel, don't issue register writes for 200 µs. Accel startup from sleep to valid data is ~10 ms; gyro needs ~30 ms from enable to drive ready.
4. FIFO and APEX share one SRAM. Default is 1 Kbyte FIFO with the rest reserved for APEX. Set APEX_DISABLE in SENSOR_CONFIG3 to grow the FIFO to 2.25 Kbytes — it isn't automatic. Do your FIFO-depth math against the mode you actually configured.
5. FIFO configuration ordering rules. Disable the sensors before writing/changing FDR_SEL (FIFO decimation, 1-in-2 up to 1-in-256). For the watermark: FIFO_WM_EN must be 0 before writing the watermark value, set a non-zero watermark before enabling it as an interrupt source, and only change the watermark while the FIFO is empty. The watermark fires only once per assertion.
6. MREG register banks. Control is split across User Bank 0 and MREG1/2/3, accessed via BLK_SEL/MADDR/M registers. Self-test, WOM thresholds, FDR, and FIFO_CONFIG5/6 live in the MREG banks — a driver that only touches Bank 0 leaves key features unconfigured. Critically, MREG access is not supported in Sleep mode or Accel LP with WUOSC — set the IDLE bit in PWR_MGMT0 first, and wait up to 10 µs after each MREG write before further access.
7. APEX ODR constraint. The accel ODR must be ≥ DMP_ODR (25/50/100/400 Hz options) for correct operation. APEX enables and DMP_ODR can be changed on-the-fly while the accel runs.
8. Wake-on-motion config. Per-axis 8-bit thresholds (ACCEL_WOM_X/Y/Z_THR in MREG1) at 1 g/256 ≈ 3.9 mg per LSB, independent of FSR, over a 0–1 g window. In WOM_CONFIG, WOM_INT_DUR/WOM_INT_MODE/WOM_MODE cannot be changed once WOM_EN=1 — program them first.
9. Absolute limits. VDD/VDDIO abs-max −0.5 V to 4 V; I/O pins −0.5 V to VDDIO + 0.5 V. Max unpowered shock 20,000g for 0.2 ms. Part-rated ESD is 2 kV HBM / 500 V CDM, latch-up JEDEC Class II at 125 °C, ±100 mA — internal ESD is not a substitute for system-level protection on exposed wearable surfaces.
How do I test it?
Work through this sequence:
- Identity: Read
WHO_AM_I— must return 0x61. Anything else is a bus/power/wrong-part problem. - Power sanity: Rails within 1.71–3.6 V; current vs. the DC table (3.5 µA sleep, 0.2/0.42/0.55 mA low-noise modes). Sleep current far above 3.5 µA usually means you're not actually in Full-Chip Sleep.
- Scale-factor check: Accel ±2/4/8/16 g ↔ 16,384/8,192/4,096/2,048 LSB/g; gyro ±250/500/1000/2000 dps ↔ 131/65.5/32.8/16.4 LSB/(°/s). Flat on the bench should read 0 g on X/Y and +1 g on Z.
- On-chip self-test: Enable
GYRO_ST_EN/ACCEL_ST_ENin theSELFTESTregister (MREG1), keep the device perfectly still (movement aborts the test), then pollST_STATUS2forGYRO_ST_DONE,GYRO_ST_PASS, per-axis*_ST_PASS, andST_INCOMPLETE. Response = output with ST on minus output with ST off, compared against factory-trimmed per-axis values in MREG3 (XA/YA/ZA_ST_DATA,XG/YG/ZG_ST_DATA). Note: the datasheet publishes no fixed numeric min/max limits — the comparison target is the per-device stored trim. Write the enable bit back to 0 to exit. - Functional checks: Exercise each axis with known gestures and confirm sign/direction; validate any APEX features (pedometer, tilt, WOM, freefall) and the accel-ODR ≥ DMP_ODR rule.
- Temperature: The temp ODR equals the higher of gyro/accel ODR — sanity-check it tracks board temperature.
Known limitation: some accel/gyro spec-table numbers carry footnotes like "expected results based on design... not tested in production" — treat the self-test as your production-grade pass gate.
How do I troubleshoot it?
Debug in this order: bus/identity → clock → power mode/config → interrupts/FIFO.
No bus communication: Check wiring, rails, and read WHO_AM_I (expect 0x61). For I²C, confirm pull-ups exist and the 1 MHz / 550 pF limits are respected. Overvoltage on any I/O pin (abs-max VDDIO + 0.5 V) is the fastest way to kill the interface.
Data never updates: Read MCLK_RDY (Bank 0, 00h, bit 3) — 0 means the internal clock isn't running and no data will appear. Check PWR_MGMT0 mode fields; if both sensors are off the chip enters OFF state (RC oscillator off) — set the IDLE bit (bit 4) to keep register access alive. Also verify your ODR fields in GYRO_CONFIG0/ACCEL_CONFIG0 aren't set to a Reserved encoding (0000–0100), which yields nominal or no ODR.
MREG writes don't stick: You're probably in Sleep or Accel LP+WUOSC — set IDLE first, and respect the 10 µs post-write wait.
Stuck or missing interrupts: Check INT_CONFIG (mode, drive, polarity — open-drain without a pull-up looks dead), INT_CONFIG0 (clear-on-read behavior), and INT_STATUS_DRDY (auto-sets on data-ready, clears when read). Remember the four possible sources: data ready, accel event interrupts, FIFO watermark, FIFO full — there's no gyro-event pin trigger.
Data looks wrong: Re-verify FSR↔scale-factor mapping and the +1 g Z convention (Z reading −1 g means your axis interpretation is inverted). Run the self-test to separate a bad MEMS element from a host-side bug.
Wedged part: Write SOFT_RESET_DEVICE_CONFIG (bit 4) or FIFO_FLUSH (bit 2) in SIGNAL_PATH_RESET (Bank 0, 02h) — write 1, wait ~1.5 µs, read back 0 — or power-cycle, then re-run the WHO_AM_I and MCLK_RDY checks.
Part page: ICM-42607-C