The ICM-42607-C is a 6-axis IMU (accel + gyro, with APEX/DMP features) whose register map is split into four banks: one directly addressable User Bank 0 (0x00-0x7F on the I2C/SPI bus) plus three indirectly addressed banks, MREG1, MREG2 and MREG3. MREG banks are reached only through six Bank 0 bridge registers. This page is organised by register group; each heading names the exact registers it covers.
Register access: BLK_SEL_W, MADDR_W, M_W, BLK_SEL_R, MADDR_R, M_R (0x79-0x7E)
MREG1/2/3 are not in the linear address space. They are accessed through six Bank 0 registers:
| Register | Address | Function |
|---|---|---|
| BLK_SEL_W | 0x79 | Select target bank for writes: MREG1 = 0x00, MREG2 = 0x28, MREG3 = 0x50 |
| MADDR_W | 0x7A | Target address within the selected bank (write path) |
| M_W | 0x7B | Data byte written to MREG |
| BLK_SEL_R | 0x7C | Select target bank for reads (same encoding as BLK_SEL_W) |
| MADDR_R | 0x7D | Target address within the selected bank (read path) |
| M_R | 0x7E | Data byte read from MREG |
Rules: MREG transfers are single-byte only (burst unsupported); after the access you must return BLK_SEL_W and BLK_SEL_R to 0x00; after an MREG write/read it can take up to 10 µs to take effect and no register access of any kind is allowed during that window. MREG access is not supported in Sleep mode or in accel low-power mode on the WUOSC clock — power the RC oscillator via the IDLE field of PWR_MGMT0 first.
Identity and reset: WHO_AM_I (75h), SIGNAL_PATH_RESET (02h)
WHO_AM_I — 0x75, read-only, reset value 0x61. Field WHOAMI [7:0] = 8-bit device ID used to verify the device; 0x61 is different from the I2C address. This is the only device-identity register; the datasheet does not document a separate variant register.
SIGNAL_PATH_RESET — 0x02, R/W, reset 0x00. Bits 7:5, 3, 1:0 reserved.
| Bit | Field | Function |
|---|---|---|
| 4 | SOFT_RESET_DEVICE_CONFIG | Full software reset; self-clearing. 0 = not enabled, 1 = enabled |
| 2 | FIFO_FLUSH | Host may only write 1 to flush the FIFO. Sequence: write 1 → wait at least 1.5 µs → read back and verify it returned to 0 |
Power and mode: PWR_MGMT0 (1Fh)
PWR_MGMT0 — 0x1F, R/W, reset 0x00. Both mode fields change on-the-fly while the sensor is on.
| Bit | Field | Settings |
|---|---|---|
| 7 | ACCEL_LP_CLK_SEL | 0 = Wake-Up oscillator (lowest power, recommended); 1 = RC oscillator |
| 4 | IDLE | 0 = chip enters OFF when both sensors off (RC osc off); 1 = RC oscillator stays powered |
| 3:2 | GYRO_MODE | 00 = off; 01 = Standby; 10 = Reserved; 11 = Low-Noise |
| 1:0 | ACCEL_MODE | 00/01 = off; 10 = Low-Power (duty-cycled); 11 = Low-Noise |
Standard mode encodings (GYRO_MODE, ACCEL_MODE): Sleep = 00,00; Standby = 01,00; Accel LP = 00,10; Accel LN = 00,11; Gyro LN = 11,00; 6-axis LN = 11,11.
Constraints: gyro needs at least 45 ms on-time; leaving OFF for any other mode requires no register writes for 200 µs; in accel LP mode some ODR/averaging combinations are disallowed (ODR 1600/800 Hz with any averaging; ODR 400 Hz with 16/32/64x averaging; ODR 200 Hz with 64x).
Block-level enable for the APEX/DMP feature set is APEX_CONFIG0 (MREG1) — enables/resets/power-saves the pedometer, tilt, SMD and free-fall engines.
Full-scale and ODR: GYRO_CONFIG0 (20h), ACCEL_CONFIG0 (21h)
Both R/W, both reset 0x06. Fields are GYRO_FS_SEL / ACCEL_FS_SEL at bits 6:5 and GYRO_ODR / ACCEL_ODR at bits 3:0; changing FS re-scales the data-register sensitivity.
GYRO_UI_FS_SEL (bits 6:5):
| Code | Range | Sensitivity |
|---|---|---|
| 0 | ±2000 dps | 16.4 LSB/dps |
| 1 | ±1000 dps | 32.8 LSB/dps |
| 2 | ±500 dps | 65.5 LSB/dps |
| 3 | ±250 dps | 131 LSB/dps |
ACCEL_UI_FS_SEL (bits 6:5):
| Code | Range | Sensitivity |
|---|---|---|
| 0 | ±16 g | 2048 LSB/g |
| 1 | ±8 g | 4096 LSB/g |
| 2 | ±4 g | 8192 LSB/g |
| 3 | ±2 g | 16384 LSB/g |
GYRO_ODR (bits 3:0): 0101 = 1.6 kHz, 0110 = 800 Hz, 0111 = 400 Hz, 1000 = 200 Hz, 1001 = 100 Hz, 1010 = 50 Hz, 1011 = 25 Hz, 1100 = 12.5 Hz. Codes 0000-0100 and 1101-1111 are Reserved.
ACCEL_ODR (bits 3:0): as above, plus 1101 = 6.25 Hz, 1110 = 3.125 Hz, 1111 = 1.5625 Hz (LP only). 1.6 kHz and 800 Hz are LN only; codes 0000-0100 are Reserved.
Filter and averaging: GYRO_CONFIG1 (23h), ACCEL_CONFIG1 (22h), TEMP_CONFIG0 (24h)
GYRO_CONFIG1 — 0x23, R/W, reset 0x02. Bits 7:3 reserved.
| Bits | Field | Settings |
|---|---|---|
| 2:0 | GYRO_UI_FILT_BW | 000 bypass; 001 = 180 Hz; 010 = 121 Hz; 011 = 73 Hz; 100 = 53 Hz; 101 = 34 Hz; 110 = 25 Hz; 111 = 16 Hz. Changeable on-the-fly |
ACCEL_CONFIG1 — 0x22, R/W, reset 0x41. Bits 7 and 3 reserved.
| Bits | Field | Settings |
|---|---|---|
| 6:4 | ACCEL_UI_AVG | LP-mode averaging: 000 = 2x, 001 = 4x, 010 = 8x, 011 = 16x, 100 = 32x, 101 = 64x, 110 = 64x, 111 = 64x. Cannot be changed while accel is in LP mode |
| 2:0 | ACCEL_UI_FILT_BW | Same encodings as GYRO_UI_FILT_BW; changeable on-the-fly |
Reset 0x41 = ACCEL_UI_AVG = 32x + ACCEL_UI_FILT_BW = 180 Hz.
TEMP_CONFIG0 — 0x24, R/W, reset 0x00. Bits 7 and 3:0 reserved; the only field is TEMP_FILT_BW (bits 6:4), on-the-fly changeable: 000 bypass; 001 = 180 Hz; 010 = 72 Hz; 011 = 34 Hz; 100 = 16 Hz; 101 = 8 Hz; 110 = 4 Hz; 111 = 4 Hz. There is no temp ODR field: the temperature ODR is the higher of the gyro and accel ODRs, so no fresh temperature is guaranteed with both sensors off.
Sensor data: TEMP_DATA, ACCEL_DATA_X/Y/Z, GYRO_DATA_X/Y/Z, TMST_FSYNC (09h-18h)
All read-only, 16-bit MSB/LSB pairs (MSB at the lower address):
| Addr | Register | Contents |
|---|---|---|
| 0x09-0x0A | TEMP_DATA1 / TEMP_DATA0 | Temperature; degrees C = TEMP_DATA/128 + 25 |
| 0x0B-0x0C | ACCEL_DATA_X1 / X0 | Accel X |
| 0x0D-0x0E | ACCEL_DATA_Y1 / Y0 | Accel Y |
| 0x0F-0x10 | ACCEL_DATA_Z1 / Z0 | Accel Z |
| 0x11-0x12 | GYRO_DATA_X1 / X0 | Gyro X |
| 0x13-0x14 | GYRO_DATA_Y1 / Y0 | Gyro Y |
| 0x15-0x16 | GYRO_DATA_Z1 / Z0 | Gyro Z |
| 0x17-0x18 | TMST_FSYNC | Timestamp / FSYNC counter |
The block 0x09-0x18 is contiguous; one burst read retrieves the whole sample.
APEX data: APEX_DATA4, APEX_DATA5 (1Dh-1Eh) and APEX_DATA0-3 (31h-34h)
| Addr | Register | Contents |
|---|---|---|
| 0x1D | APEX_DATA4 | FF_DUR[7:0] — lower byte of measured free-fall duration |
| 0x1E | APEX_DATA5 | FF_DUR[15:8] — upper byte |
| 0x31-0x34 | APEX_DATA0-3 | Step count, cadence, idle/activity |
FF_DUR is a 16-bit readback of free-fall duration in DMP samples (not a configuration field). Conversion: FF_DISTANCE = 0.5 x 9.81 x (FF_DUR x DMP_ODR_S)^2.
Interrupt pin and routing: INT_CONFIG (06h), INT_SOURCE0/3 (2Bh/2Eh), INT_SOURCE6-10
INT_CONFIG — Bank 0, 0x06, R/W, reset 0x00 (both pins active-low, open-drain, pulsed). Bits 7:6 reserved.
| Bit | Field | 0 | 1 |
|---|---|---|---|
| 5 | INT2_MODE | Pulsed | Latched |
| 4 | INT2_DRIVE_CIRCUIT | Open drain | Push-pull |
| 3 | INT2_POLARITY | Active low | Active high |
| 2 | INT1_MODE | Pulsed | Latched |
| 1 | INT1_DRIVE_CIRCUIT | Open drain | Push-pull |
| 0 | INT1_POLARITY | Active low | Active high |
INT_SOURCE0 (0x2B, reset 0x10 — only RESET_DONE routes to INT1 by default) and INT_SOURCE3 (0x2E) route UI events to INT1/INT2 via one bit per event (bit 7 ST_INT, 6 FSYNC, 5 PLL_RDY, 4 RESET_DONE, 3 DRDY, 2 FIFO_THS, 1 FIFO_FULL, 0 AGC_RDY, each with _INT1_EN/_INT2_EN form). The datasheet advises disabling FIFO_FULL_INT while reading the FIFO. INT_SOURCE6-10 live in MREG1 and route APEX (free-fall, low-g, step, tilt) and WOM/SMD events.
Interrupt status: INT_STATUS_DRDY (39h), INT_STATUS (3Ah), INT_STATUS2 (3Bh), INT_STATUS3 (3Ch)
All read-only / read-to-clear (R/C):
| Addr | Register | Reset | Flags |
|---|---|---|---|
| 0x39 | INT_STATUS_DRDY | — | bit0 DATA_RDY_INT: new data ready |
| 0x3A | INT_STATUS | 0x10 | bit7 ST_INT (self-test done), plus FIFO/PLL/reset flags |
| 0x3B | INT_STATUS2 | — | FIFO threshold / overflow flags |
| 0x3C | INT_STATUS3 | — | APEX flags incl. bit5 STEP_DET_INT (clears on read), tilt/SMD/free-fall |
Reading clears latched bits (the data-ready clear option is selectable via UI_DRDY_INT_CLEAR in MREG1).
Also MCLK_RDY at 0x00 (read-only): bit 3 indicates the main clock / PLL is ready.
FIFO: FIFO_CONFIG1 (28h), FIFO_CONFIG2 (29h), FIFO_CONFIG3 (2Ah), FIFO_COUNTH/L (3Dh/3Eh), FIFO_DATA (3Fh)
FIFO_CONFIG1 — 0x28, R/W. Bits 7:2 reserved.
| Bit | Field | Function |
|---|---|---|
| 1 | FIFO_MODE | 0 = Stream-to-FIFO (oldest overwritten when full); 1 = Stop-on-Full |
| 0 | FIFO_BYPASS | 0 = FIFO enabled; 1 = bypassed |
FIFO_CONFIG2/3 — 0x29/0x2A: 12-bit watermark FIFO_WM[7:0] / FIFO_WM[11:8]; FIFO_THS fires when the FIFO reaches it (in bytes or records per FIFO_COUNT_FORMAT). Constraints: FIFO_WM_EN must be 0 before writing the watermark; write a non-zero value before enabling FIFO_THS; change the watermark only while the FIFO is empty; the interrupt fires once per crossing until cleared.
FIFO_COUNTH/FIFO_COUNTL (0x3D/0x3E, read-only): unread byte count. FIFO_DATA (0x3F, read-only): popping reads; on a full FIFO a 0xFF value marks available/empty status unless disabled. Packet formats: [HDR][GX][GY][GZ], [HDR][AX][AY][AZ], [HDR][G XYZ][A XYZ], [HDR][G XYZ][A XYZ][TEMP]; HEADER_MSG (bit 7 of header) = 1 marks FIFO empty.
OTP control: OTP_CTRL7 (MREG2, addr 06h)
Bits 7:4, 2, 0 reserved. Writing this register casually is dangerous:
| Bit | Field | Meaning |
|---|---|---|
| 3 | OTP_RELOAD | 1 triggers an OTP copy (reloads factory trim into SRAM) |
| 1 | OTP_PWR_DOWN | 0 = power up OTP to copy OTP to SRAM; 1 = power down OTP (auto-set after copy) |
Related: OTP_CONFIG (MREG1, addr 0x2B), OTP_COPY_MODE bits 3:2 — only 01 (OTP to SRAM) and 11 (self-test data) are defined; 00 and 10 are Reserved and must not be selected.
Reserved bits and write rules
Blanket rule: reserved fields must not be modified — read-modify-write every config register and preserve reset values of reserved bits. Only fields explicitly marked on-the-fly changeable may be written while a sensor is running; everything else must not. Verified reserved examples: GYRO_CONFIG1 bits 7:3, SIGNAL_PATH_RESET bits 7:5/3/1:0, OTP_CTRL7 bits 7:4/2/0.
Bus access
Interfaces (pin-strapped): I3C SDR 12.5 MHz / DDR 25 Mbps; I2C 1 MHz (7-bit address b110100X, LSB from AP_AD0, so 0x68/0x69); SPI 24 MHz, 3- or 4-wire, slave only, 8-bit address word with MSB as R/W. Bank 0 supports burst reads/writes with address auto-increment; the MREG indirect path is single-byte only.
MREG1 contents (indirect)
TMST_CONFIG1, FIFO_CONFIG5/6, FSYNC_CONFIG, INT_CONFIG0/1, INT_SOURCE6-10 (incl. I3C IBI enables), APEX_CONFIG2-12 (pedometer/free-fall/SMD/tilt thresholds), ACCEL_WOM_X/Y/Z_THR, OFFSET_USER0-8 (accel + gyro user offsets), ST_CONFIG, SELFTEST, ST_STATUS1/2, FDR_CONFIG, OTP_CONFIG. MREG3 holds the read-only self-test results XA/YA/ZA_ST_DATA and XG/YG/ZG_ST_DATA.
Note: field tables for some registers (e.g. detailed bit layouts of INT_STATUS2 and parts of the Bank 0 map around 0x27) were not fully retrieved from the datasheet in preparing this page; where a value is not stated above, this reference does not assert one.
Part page: ICM-42607-C.