ICM-42607-C programming: always-on Wake-on-Motion configuration guide

ICM-42607-C: what is the typical use case this guide targets?

Always-on motion detection in a battery-tight wearable or hearable: the ICM-42607-C stays powered in accelerometer Low-Power (LP) mode running the on-chip Wake-on-Motion (WOM) engine, while the host MCU sleeps. When motion exceeds a per-axis threshold, the part asserts the INT1 pin to wake the host. The host services the event, optionally streams accel data, then returns to sleep. The datasheet targets exactly this: "Low-Power mode support for always-on experience."

ICM-42607-C: what must I check before writing any configuration?

Read WHO_AM_I at address 0x75. It is read-only with reset value 0x61, described as "Register to indicate to user which device is being accessed." A read returning 0x61 confirms the correct part and a working I2C/SPI link. Anything else means wrong device, wrong address, or a dead bus — do not proceed to configuration.

ICM-42607-C: what is the ordered startup sequence?

All Bank 0 registers are written directly. MREG1 registers are reached indirectly (see the next question).

1. Read WHO_AM_I (0x75) — expect 0x61. Verifies device identity and bus.
2. Write 0x06 to ACCEL_CONFIG0 (0x21) — sets ACCEL_UI_FS_SEL (bits 6:5) = 11 = ±2 g and ACCEL_ODR (bits 3:0). Note 0x06 is also the reset value of this register. For the always-on case you will instead write an LP-mode ODR into bits 3:0 — see the design-choice question below. The ODR codes 0000–0100 are Reserved; codes 0101 (1.6 kHz) and 0110 (800 Hz) are LN-mode only; codes 1101–1111 (6.25 / 3.125 / 1.5625 Hz) are LP-mode only.
3. Write 0x02 to PWR_MGMT0 (0x1F) — ACCEL_MODE (bits 1:0) = 10 = Low Power, GYRO_MODE (bits 3:2) = 00 = off, ACCEL_LP_CLK_SEL (bit 7) = 0 (wake-up oscillator, the datasheet's recommended lowest-power setting), IDLE (bit 4) = 0. This write starts the 200 µs no-write window — see the timing question.
4. Wait 200 µs — after the OFF→LP transition in step 3, issue no register writes for 200 µs.
5. Write 0x07 to INT_CONFIG (0x06) — INT1 push-pull, active-high, latched (bits 2:0 = 111). For an open-drain active-low wake line with external pull-up, write 0x04 instead.
6. Write the WOM thresholds to MREG1 via the indirect-access registers (next question): ACCEL_WOM_X_THR (0x4B), ACCEL_WOM_Y_THR (0x4C), ACCEL_WOM_Z_THR (0x4D). Each byte is a fixed threshold in mg, independent of full scale, at 1 g/256 ≈ 3.9 mg per LSB. For a ~50 mg threshold: 50 / 3.9 ≈ 12.8 → write 0x0D to each axis you monitor.
7. Write 0x01 to WOM_CONFIG (0x27, Bank 0) — WOM_EN = 1, WOM_INT_MODE = 0 (OR of enabled axes), WOM_MODE = 0 (compare against stored initial sample), WOM_INT_DUR = 00 (assert on 1st over-threshold event). The three config fields cannot be changed while WOM_EN = 1, so write the whole byte atomically. For a 2-event debounce, write 0x09 instead (WOM_INT_DUR = 01).

Not covered here: the INT_SOURCE0/INT_SOURCE1 bit that routes the WOM interrupt to INT1 could not be confirmed from the datasheet corpus. Do not guess that bit — consult the full datasheet register table for the interrupt routing register before relying on it.

ICM-42607-C: how do I write the WOM threshold registers in MREG1?

There is no REG_BANK_SEL on this part. MREG1/MREG2/MREG3 are reached through six Bank 0 pointer registers:

For MREG1: BLK_SEL_W = 0x00, BLK_SEL_R = 0x00 (MREG2 = 0x28, MREG3 = 0x50). MREG1 registers use their absolute addresses verbatim in MADDR_W — there is no base offset. The datasheet's own example: to write MREG1 register 0x14, set BLK_SEL_W = 0x00, MADDR_W = 0x14, then write the value to M_W.

So for ACCEL_WOM_X_THR: write 0x00 to BLK_SEL_W (0x79), write 0x4B to MADDR_W (0x7A), write the threshold byte to M_W (0x7B). Repeat with 0x4C and 0x4D for Y and Z.

Hard rules from the datasheet: after any MREG access, restore BLK_SEL_W and BLK_SEL_R to 0x00, and only single-byte transfers are allowed for these indirect accesses — no burst.

ICM-42607-C: which values are required and which are design choices?

Effectively fixed by this use case: ACCEL_MODE = 10 (LP) and GYRO_MODE = 00 (off) in PWR_MGMT0, and IDLE = 0 — the datasheet says "nominally this bit is set to 0"; setting it powers the RC oscillator even with both sensors off, defeating the low-power goal.

Design choices and the trade-offs the datasheet states:

• ACCEL_UI_FS_SEL (±2/4/8/16 g): the datasheet states no power trade-off for this field; it only picks full-scale range. Choose the range that covers your worst-case acceleration without clipping.
• ACCEL_ODR: responsiveness vs. power. Codes 1101–1111 (6.25 / 3.125 / 1.5625 Hz) are LP-mode only — the lowest-power always-on rates at the cost of latency. LP mode bans these ODR/averaging combinations: 1600 or 800 Hz with any averaging; 400 Hz with 16×/32×/64×; 200 Hz with 64×. At 25 Hz and below, every averaging factor from 1× to 64× is legal.
• ACCEL_LP_CLK_SEL: 0 = wake-up oscillator, "lowest power consumption mode… the recommended setting"; 1 = RC oscillator, higher power. Note that 0 is also the reset default — PWR_MGMT0 resets to 0x00, so bit 7 already powers up at the recommended wake-up-oscillator setting and you only need to write it if you deliberately want the higher-power RC oscillator (bit 7 = 1).
• ACCEL_WOM_X/Y/Z_THR: lower threshold catches faint motion but causes more false wakes; higher threshold means fewer false wakes but you may miss small motions. Resolution is fixed at ≈3.9 mg per LSB regardless of full scale.
• INT_CONFIG INT1 fields: pulsed vs. latched, open-drain vs. push-pull, polarity — match your host's wake-line expectations. Latched holds the assert until serviced.
• WOM_INT_DUR / WOM_INT_MODE / WOM_MODE: assertion debounce (1st–4th event), OR vs. AND across axes, initial-sample vs. previous-sample comparison.

Compliance rule, not a knob: if you ever enable the gyro, it must stay ON for a minimum of 45 ms before it is considered settled. Irrelevant to the accel-only WOM case.

ICM-42607-C: what delays or waits are required between steps?

The datasheet states two explicit timing rules, both in the PWR_MGMT0 description:

1. 200 µs no-write window: "When transitioning from OFF to any of the other modes, do not issue any register writes for 200 µs." This applies to the step-3 write that sets ACCEL_MODE = 10. Do not write INT_CONFIG, the WOM thresholds, or WOM_CONFIG until it elapses.
2. 45 ms gyro minimum ON time: only if you enable the gyro. Not applicable here.

The datasheet's A.C. Electrical Characteristics table (Table 4), which would carry detailed startup-time parameters, was not recoverable in full — no additional settling numbers can be cited beyond the two above.

Separately, SIGNAL_PATH_RESET (0x02) FIFO flush has a defined verify sequence: "Write FIFO_FLUSH = 1; Wait for 1.5 µs; Read FIFO_FLUSH, it should now be 0."

ICM-42607-C: how does firmware read results back?

Accelerometer data lives in six read-only Bank 0 registers, signed 16-bit split high/low per axis:

Reassemble as (high << 8) | low, two's-complement, scaled to the configured full scale.

Two response patterns:

• WOM always-on (this use case): the host does not poll. It sleeps; on over-threshold motion the part asserts INT1. The host then reads INT_STATUS to identify the source, optionally reads the data registers, and re-enters sleep.
• Polled streaming: check the DATA_RDY_INT flag in INT_STATUS_DRDY (Bank 0), then read 0x0B–0x10. Clearing behavior is configured via UI_DRDY_INT_CLEAR in INT_CONFIG0 (MREG1, 0x04) — its exact encodings were not confirmed from the corpus, so treat them as unverified.

ICM-42607-C: how do I verify the configuration took?

1. WHO_AM_I (0x75) == 0x61 — correct part, working bus.
2. Read back config writes: PWR_MGMT0 should read 0x02; ACCEL_CONFIG0 should read what you wrote (its reset value is 0x06, so an unmodified write still reads 0x06). The datasheet formalizes this: "The Reset Value of the register can be used to determine the default value of reserved register fields, and unless otherwise noted this default value must be maintained." A mismatch means the write path is broken.
3. Verify MREG1 writes via the read path: set BLK_SEL_R = 0x00, MADDR_R = 0x4B/0x4C/0x4D, read M_R — each should equal the threshold byte you wrote. Single-byte transfers only.
4. Self-clear check (optional bus-alive test): the SIGNAL_PATH_RESET FIFO_FLUSH write-then-read-back-to-0 sequence above.
5. Functional proof: after configuration, motion beyond the threshold asserts INT1 (latched, per INT_CONFIG), and the data registers 0x0B–0x10 return valid non-reset samples.

ICM-42607-C: what are the common failure modes?

• Writing within 200 µs of the OFF→LP transition — a spec violation; the datasheet states it verbatim on both ACCEL_MODE and GYRO_MODE.
• Entering LP mode with an illegal ODR: LN-only ODR codes (1.6 kHz, 800 Hz) contradict ACCEL_MODE = 10; Reserved codes 0000–0100 are undefined.
• IDLE = 1: powers the RC oscillator with both sensors off, defeating the always-on power goal.
• LP mode without honoring ACCEL_LP_CLK_SEL: the ACCEL_MODE description explicitly says "When selecting LP Mode please refer to ACCEL_LP_CLK_SEL setting, bit[7] of this register."
• Trying to change WOM_INT_DUR/WOM_INT_MODE/WOM_MODE while WOM_EN = 1: only WOM_EN itself is changeable while enabled; write the byte atomically.
• Burst transfers on the indirect MREG access registers: only single-byte transfers are allowed.
• Leaving BLK_SEL_W/BLK_SEL_R non-zero after an MREG access — the datasheet requires restoring them to 0x00.

ICM-42607-C: what is still unverified?

The following could not be confirmed from the datasheet corpus and must be pulled from the full register table before firmware depends on them: the INT_SOURCE0/INT_SOURCE1 routing bit for WOM → INT1, the ACCEL_CONFIG1 ACCEL_UI_AVG binary encodings, the UI_DRDY_INT_CLEAR encodings, and the full INT_STATUS bit map. Per-ODR current figures in LP mode were also not recoverable — validate actual draw on your bench before locking the battery budget.

Part page: ICM-42607-C.