The HLW8110 (Hiliwei HLW811x family) is a single-phase energy-metering IC with a 16-bit, 100 kS/s ADC front end, accessed over SPI or UART. Its register space is a linear 7-bit address range (00H-77H) with no bank-select or paging: calibration/configuration registers at 00H-13H (all write-protected), read-only metrological results at 20H-2FH, peak registers at 30H-32H, instantaneous/waveform registers at 38H-3FH, and interrupt/system registers at 40H onward. There is no WHO_AM_I or device-identity register; identification is by the UART command protocol, not a readable ID field.
Calibration and configuration registers: SYSICON (00H), EMUCON (01H), HFCnst (02H), Pastart/Pbstart (03H/04H), PAGain/PBGain (05H/06H), EMUCON2 (13H), ...
All registers in 00H-13H are read/write and write-protected: send the write-enable command (0xEA 0xE5) before writing, and 0xEA 0xDC to re-lock afterwards.
SYSICON - System Control Register, 0x00H, reset 0A04H
| Bits | Field | Meaning |
|---|---|---|
| 15-12 | NC | Reserved; keep at reset value |
| 11 | ADC3ON | 1 = voltage channel U open (enabled); 0 = closed |
| 10 | ADC2ON | 1 = current channel B open; 0 = closed |
| 9 | ADC1ON | 1 = current channel A open; 0 = closed |
| 8-6 | PGAIB[2:0] | Channel B PGA gain: 1XX = 16, 011 = 8, 010 = 4, 001 = 2, 000 = 1 |
| 5-3 | PGAU[2:0] | Voltage channel U PGA gain (same mapping) |
| 2-0 | PGAIA[2:0] | Channel A PGA gain (same mapping) |
PGA gain sets each channel's full-scale input (with the internal 1.25 V reference): PGA 1 = 800 mV peak (~566 mV RMS), 2 = 400 mV, 4 = 200 mV, 8 = 100 mV, 16 = 50 mV (~35.4 mV RMS).
EMUCON - Energy Measure Control Register, 0x01H, reset 0000H
| Bits | Field | Meaning |
|---|---|---|
| 15-14 | Tsensor_Step[1:0] | Temperature-sensor measurement step (4-phase chopping offset sequence) |
| 13 | tensor_en | 0 = close / 1 = open the temperature measurement module |
| 12 | comp_off | 0 = comparator module working / 1 = closed (comparator and channel-B current measurement are exclusive) |
| 11-10 | Pmode[1:0] | Active-power calc mode: 00 = algebraic sum (both polarities, REVQ flag); 01 = positive only accumulated; 10 = absolute-value sum, no reverse flag; 11 = reserved (treated as 00) - do not write |
| 9 | DC_MODE | 0 = normal AC RMS mode; 1 = through (DC) mode - turns off self-multiplication, LPF and open-side operation; requires WaveEN = 1 first |
| 8 | ZXD1 | 0 = ZX changes only at selected zero-crossing; 1 = ZX toggles at both + and - crossings |
| 7 | ZXD0 | 0 = forward / 1 = negative zero-crossing as detection point |
| 6 | HPFIBOFF | Channel-B current digital HPF: 0 = open (AC), 1 = closed (DC measurement) |
| 5 | HPFIAOFF | Channel-A current digital HPF: 0 = AC, 1 = DC |
| 4 | HPFUOFF | Voltage-channel U digital HPF: 0 = AC, 1 = DC |
| 3-2 | NC | Reserved |
| 1 | PBRUN | 1 = on: PFB pulse output + Energy_PB accumulation; 0 = off (default) |
| 0 | PARUN | 1 = on: PFA pulse output + Energy_PA accumulation; 0 = off (default) |
Other calibration-bank registers (00H-13H)
| Register | Addr | Reset | Notes |
|---|---|---|---|
| HFCnst | 0x02H | 1000H | HFConst; write-protected |
| Pastart | 0x03H | 0060H | Channel-A start-power threshold; write-protected |
| Pbstart | 0x04H | 0060H | Channel-B start-power threshold; write-protected |
| PAGain | 0x05H | 0000H | Active-power channel-A gain correction, 16-bit W/R |
| PBGain | 0x06H | 0000H | Active-power channel-B gain correction, 16-bit W/R |
| PhaseA / PhaseB | 0x07H / 0x08H | - | Phase calibration; write-protected |
| PA0S / PB0S | 0x0AH / 0x0BH | - | Active & apparent power offset calibration, 16-bit W/R |
| RmsIAOS / RmsIBOS | 0x0EH / 0x0FH | - | RMS offset calibration; write-protected |
| IbGain | 0x10H | - | Channel-B gain; write-protected |
| PSGgain | 0x11H | 0000H | Apparent-power gain correction, 16-bit W/R |
| PSOS | 0x12H | - | Apparent-power offset; write-protected |
EMUCON2 - Energy Measure Control Register 2, 0x13H, reset 0001H
| Bit | Field | Meaning |
|---|---|---|
| 5 | WaveEN | Master waveform-enable; must be set before ZxEN, PeakEN and DC_MODE |
| 2 | ZxEN | 1 = enable zero-crossing detection, phase-angle and voltage-frequency measurement (requires WaveEN = 1) |
| 1 | PeakEN | 1 = enable peak detection (requires WaveEN = 1) |
| 0 | VrefSel | 1 = select built-in 1.25 V reference |
Metrological result registers: RmsIA (24H), RmsIB (25H), RmsU (26H), PF (27H), E_PA (28H), E_PB (29H), ...
All read-only. Fast active-power pulse counters and the voltage-frequency register also live in this bank (20H-23H):
| Register | Addr | Size / format | Meaning |
|---|---|---|---|
| PFCnt_PA | 0x20H | 16-bit, W/R, reset 0000H | Fast active-power pulse counter, channel A |
| PFCnt_PB | 0x21H | 16-bit, W/R, reset 0000H | Fast active-power pulse counter, channel B |
| Ufreq | 0x23H | 16-bit, R, reset 0000H | Voltage frequency: f = CLKI / 8 / Ufreq (e.g. 3.579545 MHz / 8 / 8948 = 49.99 Hz); updated every 0.7 s |
| RmsIA | 0x24H | 24-bit | Current channel-A RMS; bit 23 = valid-data flag |
| RmsIB | 0x25H | 24-bit | Current channel-B RMS; bit 23 = valid-data flag |
| RmsU | 0x26H | 24-bit | Voltage RMS |
| PF | 0x27H | 24-bit signed | Power factor (channel A or B per channel_sel) |
| E_PA | 0x28H | 24-bit | Active power, channel A |
| E_PB | 0x29H | 24-bit | Active power, channel B |
| PowerA | 0x2CH | 32-bit two's-complement | Average active power, U x IA |
| PowerB | 0x2DH | 32-bit two's-complement | Average active power, U x IB |
| PowerS | 0x2EH | 32-bit two's-complement | Average apparent/active power of U with A or B (per channel_sel) |
| EMUStatus | 0x2FH | 24-bit (lower 16 used) | Meter status: channel_sel, no-load (NopldA/B), reverse-power (REVPA/B), checksum-busy flags; also stores the 16-bit checksum of registers 00H-1FH (double-byte accumulation, byte-swapped; equals 0xB32E at defaults) |
Conversion formulas (Section 10): current = RmsIA x RmsIAC / 2^23 (A); voltage = RmsU x RmsUC / 2^23 (V); power = PowerXX x PowerXXC / (K1 x K2 x 2^31) (W), where K1 is the current-sensor gain and K2 the voltage-divider ratio. Coefficients RmsIAC/RmsIBC live at 0x70H/0x71H in the Coefficient register block.
Peak registers: PeakIA (30H), PeakIB (31H), PeakU (32H)
All 24-bit, read-only, reset 000000H, clear-on-read. The master map calls them PeakA/PeakB/PeakU; Table 34 and Section 8.10 call them PeakIA/PeakIB/PeakU - same three registers.
| Register | Addr | Meaning |
|---|---|---|
| PeakIA / PeakA | 0x30H | Peak of current channel A |
| PeakIB / PeakB | 0x31H | Peak of current channel B |
| PeakU | 0x32H | Peak of voltage channel U |
Behaviour: continuous max-hold - a register updates whenever the absolute waveform value exceeds the stored value. Reading a peak register clears it and restarts peak measurement. After reading, wait at least 10 ms before reading again, or the value is not guaranteed to be the true half-cycle peak. Requires WaveEN = 1 then PeakEN = 1 in EMUCON2.
Instantaneous value and waveform registers: InstanP (3CH), InstanS (3DH), ... (38H-3FH)
Read-only instantaneous samples and waveform data.
| Register | Addr | Size / format | Meaning |
|---|---|---|---|
| WaveU | 0x38H | - | Voltage channel waveform sample |
| InstanP (PowerP) | 0x3CH | 4-byte, R | Instantaneous active power |
| InstanS (PowerS) | 0x3DH | 4-byte, R | Instantaneous apparent power (companion to InstanP; the average counterparts are PowerA/PowerB at 2CH/2DH and average PowerS at 2EH) |
The waveform-sample registers earlier in the block (Section 9.4 also lists WaveIA at 0x36H, WaveIB at 0x37H, and WaveU at 0x38H); individual addresses beyond 0x3DH in 0x38H-0x3FH follow the same per-channel waveform-sample pattern in the datasheet's master register map and Section 9.4.
Interrupt registers: IE (40H), IF (41H), RIF (42H)
| Register | Addr | Access | Meaning |
|---|---|---|---|
| IE | 0x40H | W/R | Interrupt enable/config; admits flags into IF. Write enable (0xEA 0xE5) must be opened before configuring this register. |
| IF | 0x41H | R, clears-on-read | Pending interrupt flags: LeakageIF [15], ZX_UIF [14], ZX_IBIF [13], ZX_IAIF [12], SAGIF [11] (undervoltage), OPIF [10] (power overload), OVIF [9], OIBIF [8], OIAIF [7], INSTANIF [6], PEBOIF [4], PEAOIF [3], PFBIF [2], PFAIF [1], DUPDIF [0]. Bit 5 is not a defined flag. |
| RIF | 0x42H | R, clears-on-read | Reset-interrupt flag, mirror of IF; reading it clears both IF and RIF together |
System status and coefficient registers: SysStatus (43H), CheckSum (6FH), RmsIAC (70H), ... EnergyBC (77H)
| Register | Addr | Access | Meaning |
|---|---|---|---|
| SysStatus | 0x43H | R | System status: clksel (bit 6, internal vs external crystal), WREN (bit 4, write-enable flag), RST (bit 0, reset-occurred flag - set after any reset including external RST_N pin, cleared by reading) |
| CheckSum | 0x6FH | - | First word of the 16-bit-per-entry Coefficient register block (0x6F-0x77) |
| RmsIAC ... EnergyBC | 0x70H-0x77H | - | Calibration coefficients incl. RmsIAC (0x70H), RmsIBC (0x71H), power coefficients; ends with EnergyBC and CheckSum coverage |
Reset triggers (Section 8.1): power-on reset (on-chip threshold 2.9 V, power-off 2.7 V, 0.2 V hysteresis), low-voltage (brown-out) reset, software reset via the instruction 0xEA 0x96 (completes after two system clocks), and the external RST_N pin. On any reset all registers return to initial values. There is no register you write to reset the device.
Access protocol and write protection
- Command byte: bit 7 = direction (0 = read, 1 = write), bits [6:0] = 7-bit register address. Special commands are the fixed byte 0xEA followed by a second byte: 0xE5 = write enable, 0xDC = write protect (close), 0x5A = select channel A, 0xA5 = select channel B, 0x96 = software reset.
- Every writable register in 00H-13H plus IE (0x40H) is write-protected; open write access with 0xEA 0xE5 before any write burst and close with 0xEA 0xDC.
- Ordering: write-enable before any config write; WaveEN = 1 before ZxEN, PeakEN or DC_MODE.
- Reserved/NC bits (SYSICON 15-12, EMUCON 3-2, IF bit 5, Pmode = 11): write as 0 / do not use.
- Multi-byte registers stream highest byte first, low byte last, MSB-first within bytes. No cross-register burst/auto-increment; each register is addressed individually.
- SPI: SCLK range 0.11 kHz to 0.895 MHz; host clocks command on SCLK rising edge, slave drives SDO on SCLK rising edge; data-byte time T1 >= 1/2 SCLK period; two SCLK rising edges must not be more than 9.15 ms apart (SPI watchdog). Timing parameters t1/t2 >= 0.5 x Tsclk (~559 ns at max clock); t3-t8 have no published numeric values (Figure 31 annotations only).
- UART: fixed 9600 baud (HLW8110), half-duplex, 9-bit frames (8 data + 1 check bit), slave mode. Selected by power-up straps: SPIEN = 1 selects SPI (any SCLK/SCSN); SPIEN = 0, SCLK = 1, SCSN = 0 gives UART at 9600. Each frame carries a checksum: one's complement of the running byte sum, low 8 bits. Worked write of 1234H to 02H: frames 0xA5, 0x82, 0x12, 0x34, then check 0x92 = ~(A5+82+12+34) low byte.
- After writing calibration registers, verify the checksum in EMUStatus (0x2FH) - it equals 0xB32E at defaults - rather than trusting a blind write.
Troubleshooting
- Writes appear to do nothing: write access was not opened. Send 0xEA 0xE5 first; all of 00H-13H and IE (0x40H) are write-protected. Re-lock with 0xEA 0xDC when done.
- Zero-crossing, peak detection or DC mode not working: WaveEN (EMUCON2, 0x13H) must be set to 1 before ZxEN, PeakEN or DC_MODE.
- SysStatus RST bit set: that is the reset-occurred flag, set after any reset (power-on, brown-out, software instruction 0xEA 0x96, or external RST_N pin) and cleared by reading. It is not an error indication by itself.
- Peak values look wrong or zero: each read clears the peak register and restarts tracking; wait at least 10 ms between reads, and confirm PeakEN (and WaveEN) are set.
- Suspected calibration corruption: read the checksum in EMUStatus (0x2FH); at default register values it must read 0xB32E.
- IF bit 5 reads set: bit 5 of IF is not a defined flag; mask it in software.
- SPI communication drops: check the 9.15 ms maximum gap between SCLK rising edges (watchdog reset) and the 0.895 MHz SCLK limit; interface selection (SPIEN/SCLK/SCSN straps) is latched at power-up and cannot be changed mid-operation.
Part page: HLW8110.