The FT4232H is a single-chip USB 2.0 High-Speed (480 Mb/s) to quad-serial bridge from FTDI: it gives you four independent channels, each configurable as a UART (up to 12 Mbit/s, RS232/RS422/RS485 with a TXDEN auto-transmit pin) or — on channels A and B only — as an MPSSE engine that implements JTAG, SPI, I²C, or bit-bang at up to a sustained 30 Mbit/s. The entire USB protocol runs on-chip, so there is no device-side USB firmware to write, and royalty-free VCP and D2XX drivers mean most designs need no custom driver work either. Typical applications in the datasheet read like a menu: USB to 4× UART, 2× JTAG + 2× UART, 1× SPI + 1× JTAG + 2× UART, 2× I²C + 2× UART, and several more combinations — essentially any design that needs to move several serial or synchronous-serial links over one USB connection. This post walks through the whole bring-up sequence: wiring and powering the part, the datasheet defaults and quirks that trip people up, how to verify a fresh board, and where to look when something doesn't work.
How do I wire it up?
The reference shape of the design is simple: USB 2.0 High-Speed and a 12 MHz crystal feed the part; a serial EEPROM holds its configuration; four channel interfaces come out the other side:
- Channel A: MPSSE (SPI/I²C/JTAG) or UART
- Channel B: MPSSE or UART
- Channel C: UART
- Channel D: UART, or RS485 via TXDEN
Clock. Use a 12 MHz ±0.003% parallel-cut crystal with loading capacitors from OSCI/OSCO to GND — 27 pF is shown as an example, but tune to your crystal vendor's recommendation. Alternatively, drive OSCI from a 12 MHz CMOS-output oscillator and leave OSCO unconnected. No clock means no USB enumeration, so this is the first thing to confirm on a dead board.
USB pair. The part handles USB 2.0 High Speed (480 Mb/s) with Full-Speed (12 Mb/s) fallback. The datasheet's reference application figure for the bus-powered configuration shows a 91/12 kΩ DM/DP pull-up network — follow that value pair for the USB PHY pull-up. The PHY also requires a 12 kΩ resistor between REF and GND on the PCB; that's an explicit, datasheet-mandated external component, and the PHY won't bias correctly without it. The datasheet itself does not publish PCB layout rules for DP/DM (no target impedance, no length-matching figure) — it points you to TN 166 "FTDI Example IC Footprints" for layout. Treat the pair as a high-speed differential link regardless; it's a 480 Mb/s SERDES, not a loose logic line.
EEPROM. The configuration EEPROM must be 16-bit wide and capable of 1 Mbit/s at 3.0–3.6 V — e.g. Microchip 93LC46B/56/66 (93LC56BT in the reference design). FTDI's reference circuit uses 10 kΩ pull-ups on the DATA/CLK lines and 2 kΩ on CS#. It's programmed in-circuit over USB with FT_PROG, so you can solder a blank part and program it during manufacturing.
Packages. The QFN-64 and VQFN-56 have a bottom-side central solder pad that is the device's internal ground and must be connected to system ground — it's a functional connection, not just thermal. The VQFN-56's pad is 5.90 × 5.90 mm. The LQFP-64 has no pad; its grounds are the peripheral pins only. For footprints and stencil geometry, the datasheet points to TN 166.
What do I power it with, and what do I watch out for?
This is where most of the FT4232H's sharp edges live. The part has a split supply scheme you must wire exactly right:
- VCCIO (I/O cells): 2.97–3.63 V, typ 3.3 V. The datasheet states explicitly that failure to connect all VCCIO pins results in device failure — on a 64-pin part, it's easy to leave one floating.
- VREGIN: 3.0–3.6 V input to the on-chip +1.8 V LDO, which outputs VREGOUT at 1.71–1.89 V and is rated up to 150 mA.
- VCORE: 1.62–1.98 V (typ 1.8 V). Critically, there is no direct internal connection from VREGOUT to the internal functions — the PCB must route VREGOUT to the pins that require +1.8 V, including VREGIN, with a minimum 3.3 µF filter capacitor between VREGOUT and VCORE.
- VPHY/VPLL: 3.0–3.6 V. VPHY cannot be connected directly to the USB supply — it needs a +3.3 V regulator, and FTDI recommends LC-filtering both VPHY and VPLL.
The datasheet mandates that LC-filter topology but does not publish the specific L and C values — those are your choice. The one exact filter value it does give is the 3.3 µF VREGOUT→VCORE capacitor.
For budgeting: core draw is 70 mA typ in normal operation (5 mA in reset, 500 µA in USB suspend), and the PHY is 30 mA typ / 60 mA max at 480 Mb/s. The datasheet does not publish a total VCCIO current figure — VCCIO feeds the I/O driver cells, so its draw is the sum of your per-pin loads, bounded by 16 mA max per output. The default EEPROM configuration sets Max Bus Power Current = 500 mA, so a fully bus-powered design can assume up to 500 mA from the bus.
On voltage tolerance, the split matters: the serial I/O cells are 3.3 V with 5 V-tolerant inputs (DC input −0.3 to +5.8 V), but the USB PHY pins are not 5 V tolerant — DC input on USBDP/USBDM is −0.5 to +3.63 V, and that's the ceiling your ESD/overvoltage protection has to guarantee. VCORE's absolute maximum is +2.0 V. Other absolute maxima: VCCIO −0.3 to +4.0 V, all other inputs −0.5 to (VCCIO + 0.5) V, ambient −40 to +85 °C, T_J max 125 °C. Thermal Θ_JA is 29.67 °C/W for the QFN and 37.66 °C/W for the LQFP — the exposed pad is what buys the QFN its better figure.
On logic levels: VIH ≥ 2.0 V, VIL ≤ 0.8 V, and VOH at 4 mA drive is only 2.4 V min — if you drive a load expecting a clean 3.3 V high, confirm 2.4 V meets that input's VIH. Internal pull-ups/pull-downs are weak (40–190 kΩ, typ 75 kΩ) with 15–85 µA input leakage, so size external strapping resistors deliberately on critical lines like the EEPROM interface. Drive strength is configurable (4, 8, 12 or 16 mA) along with slew rate — set it per rail to match your load and EMI budget. One assembly note: the packages are MSL Level 3 with a 168 h floor life out of bag; if exceeded, bake at +125 °C up to 17 h before assembly.
Known limitation: The datasheet does not publish specific decoupling capacitor values for the supply rails, nor LC values for the VPHY/VPLL filters, nor USB differential-pair impedance/layout targets. The µF-per-rail + 100 nF-per-pin decoupling practice and differential-pair impedance goals come from engineering practice, not datasheet numbers.
How do I test it?
Work through this sequence on a fresh board:
1. Power-on sanity, before USB. Measure each rail in-band: VCCIO 2.97–3.63 V, VCORE 1.62–1.98 V, VREGIN 3.0–3.6 V, VREGOUT 1.71–1.89 V. Confirm every VCCIO pin is tied and that VREGOUT is actually routed to VCORE. Scope the 12 MHz crystal — no clock, no enumeration.
2. First enumeration against the known default. With a blank or absent EEPROM, the part defaults to serial ports with VID 0403, PID 6011, and no serial number. So the very first plug-in on a fresh board should yield four COM ports with that VID/PID. Anything else — "Unknown Device", a failed enumeration, an unexpected PID — means check power and clock before suspecting anything else.
3. Program and verify the EEPROM over USB. Use FT_PROG to program in-circuit, then power-cycle or re-plug and confirm the device enumerates with your custom VID/PID and serial number. Remember the blank-part defaults (next section) — verify each feature you need actually flipped on.
4. Driver-level confirmation. The datasheet documents royalty-free VCP and D2XX drivers for Windows, Linux, Android, macOS/OS-X, and Windows CE. If a driver fails to load, the datasheet's own pointer is TN 104, "Guide to Debugging Customers Failed Driver Installation."
5. Per-channel loopback. Jumper TXD → RXD on each of the four channels and run a pattern at your target baud. Note the datasheet explicitly says baud rates of 7, 9, 10 and 11 Mbaud are not supported even though the top rate is 12 Mbit/s — test at a supported rate.
6. MPSSE check on channels A and B. Drive a synchronous transaction and check timing against the datasheet's MPSSE table at CLKOUT = 30 MHz: t1 = 33.33 ns period, t2/t3 = 15 ns min high/low, t4 = 1–7.15 ns CLKOUT→data-out delay, t5 = 0 ns hold, t6 = 11 ns min data-in setup. The tightest number at full speed is t6 — how fast your target's outputs must be valid before the clock edge. CLKOUT can be divided internally for slower clocks, which relaxes these constraints. If you need clock-stretching masters (e.g. JTAG targets with RTCK), note that adaptive clocking is not enabled by default — enable it per AN108.
7. Suspend and remote-wake. For bus-powered designs, put the host to sleep and verify the part enters USB suspend (core drops to 500 µA). RI# low wakes the host in ~20 ms — but only if remote wake-up was enabled in the EEPROM, which it is not by default.
Why doesn't it work? Troubleshooting the usual failures
The datasheet consistently splits symptoms into two classes, and that split is the fastest diagnostic path: if the device enumerates but does the wrong thing, it's almost always an EEPROM default — reprogram and re-test before touching hardware. If it doesn't enumerate at all, it's hardware (power, clock, USB pair).
- No ports or "Unknown Device" on first plug-in: check whether you actually have a blank/no EEPROM. The unconfigured signature is specific — four serial ports, VID 0403h, PID 6011h, no serial number. If your board shows anything other than that, it's not behaving as an unconfigured part; look at hardware first.
- No COM ports after configuration: if you set the device for D2XX only, it won't enumerate as COM ports — that's expected, not a fault.
- RS485 auto-TX, remote wake, or strong drive not working: all three are disabled by default on a blank part — Remote Wake-Up, RI/RS485 TXDEN, and High-Current I/O must each be explicitly enabled in FT_PROG. Check the EEPROM setting, not the circuit.
- Failed driver installation: go to TN 104, the datasheet's own debugging guide for this exact problem.
- EEPROM appears faulty: verify the part is 16-bit wide and runs at 1 Mbit/s at 3.0–3.6 V — a wrong-width or too-slow EEPROM looks exactly like an EEPROM fault.
- Device dead from power-on: the highest-risk items on a fresh layout, in order, are the +3.63 V USB PHY ceiling (is DP/DM protected?), all VCCIO pins connected, VREGOUT actually routed to VCORE, and VCORE held at or below the 2.0 V absolute max.
Part page: FT4232H.