ADS1255: It's Not 'Just an SPI ADC' — Settling Myths and Bring-Up Tips

The ADS1255 is a 24-bit delta-sigma ADC from Texas Instruments built for high-resolution sensor measurement — a 4th-order delta-sigma modulator with a programmable digital filter, a flexible input MUX (2 differential or single-ended channels), a selectable input buffer, and a low-noise PGA with gains of 1 to 64 in binary steps. Its headline application is weigh scales, but the feature set covers bridge/sensor conditioning generally, including built-in sensor-integrity check circuitry. It shares one datasheet with the pin-compatible, higher-channel-count ADS1256 — this guide covers the ADS1255-specific limits (3 analog inputs, 2 GPIOs, 20-pin SSOP) that differ between the two parts.

The myth: "It's a 24-bit delta-sigma ADC, so I'll treat it like any other SPI peripheral — wire it up, read data, discard a few samples after channel changes, and I'm done."

The reality: The ADS1255 settles in a single cycle when a conversion is properly started (after a sync or a MUX change followed by SYNC/WREG), so no extra wait is needed — though if you switch the MUX on-the-fly during free-running continuous conversion without restarting the filter, the next sample is a mix of old and new inputs and must be discarded. Meanwhile, the real traps are elsewhere: a SYNC/PDWN pin that silently powers the chip down, a buffer that shrinks your input range, and a MUX register that happily accepts channel codes that don't exist on this part. Let's go through it properly.

What the ADS1255 actually is

The ADS1255 is a 24-bit delta-sigma ADC with a 4th-order modulator, an input buffer, and a PGA with gains of 1 to 64, plus built-in sensor-integrity check circuitry. The sensor-detect current sources (~0.5 µA, 2 µA, or 10 µA, selectable via SDCS1/SDCS0 in the ADCON register) are what back the "sensor-integrity check circuitry" — they exist specifically to verify the attached sensor is present and in range. Peak noise-free resolution is 23.0 bits at 2.5 SPS with PGA = 1, falling with data rate (22.3 bits @ 5 SPS, 20.9 @ 100 SPS, 17.1 @ 30,000 SPS). These are the datasheet's noise-free resolution figures (Table 3, buffer on, PGA = 1) — calculated from peak-to-peak noise, and distinct from the higher rms-based ENOB figures (e.g. 25.3 bits @ 2.5 SPS). They are condition-sensitive: they assume the stated test conditions (AVDD = +5 V, DVDD = 1.8 V, f_CLKIN = 7.68 MHz, V_REF = 2.5 V, −40 to +85 °C) and the buffer-on state (buffer-off values differ, e.g. 21.1 bits @ 100 SPS). It also supports fast channel cycling for multiplexed inputs and one-shot conversions that settle in a single cycle.

ADS1255-specific gotchas vs. the ADS1256 (they share one datasheet, but they are not identical):

• Only three analog inputs: AIN0, AIN1, AINCOM — one differential pair or two single-ended channels. The datasheet is explicit: only select the available inputs when programming the MUX register. Writing ADS1256-only channel codes is a real bug.
• Only two GPIOs (D0/D1), versus four on the 1256.
• 20-pin SSOP package (ADS1255IDBR and friends); the 1256 is 28-pin.
• Leave unused analog input pins floating to minimize leakage.

How to integrate it

Power and grounding. Use a small ceramic in parallel with a larger tantalum or low-voltage ceramic, close to the supply pins; the basic connection shows 0.1 µF on AVDD and 0.1 µF on DVDD. Run digital logic at as low a voltage as practical to reduce coupling into the analog inputs. Use a single ground plane for analog and digital — but keep noisy digital components off it. If you split the plane, tie the planes together; there must be no voltage difference between AGND and DGND.

Digital pins. Add ~100 Ω series resistors to control trace impedance and avoid ringing. Tie unused RESET and SYNC/PDWN pins directly to DVDD.

The reference — your most likely performance limiter. Bypass the reference inputs with low-ESR caps, as large as possible. Use a very low-noise, low-drift reference that can drive the inputs directly; if yours can't (high output impedance, resistive dividers), buffer it. The datasheet's Figure 26 circuit uses an OPA350 as a unity-gain buffer: a 10 kΩ series resistor and 1 µF cap into the non-inverting input (from a 2.5 V reference), output filter caps of 47 µF, 0.1 µF, and 100 µF to ground, output tied directly to VREFP, and the OPA350 running from +5 V with a 0.1 µF decoupling cap. Keep reference pins within AGND − 100 mV to AVDD + 100 mV (ESD diode bound).

Analog inputs. A simple RC filter limits high-frequency noise near the modulator frequency. Figure 25's starting values are 1 kΩ series / 10 nF to ground per input. Use high-grade dielectrics (low-grade ones add drift and leakage), keep traces short, place parts close to the pins, and filter every channel you use.

Clock. With a crystal, load XTAL1/XTAL2 with 5–20 pF caps to ground. Never drive other logic from the XTAL pins — share the clock via D0/CLKOUT instead. For an external clock, feed XTAL1/CLKIN and leave XTAL2 floating; keep it clean, because overshoot and glitches degrade performance.

What to watch out for

1. The buffer input-range window. With the buffer enabled, analog inputs (and reference inputs during self gain calibration) must stay between AGND and AVDD − 2.0 V. Exceeding it degrades linearity — you'll see compression near the top of range and blame the ADC.
2. Buffer-off input impedance. With the buffer off, effective input impedance drops with PGA gain — 260 kΩ/220 kΩ at PGA=1 down to 8 kΩ/7 kΩ at PGA≥32. Your source + filter resistance must stay well below this or you add gain error. Buffer on, it's high (80 MΩ at ≤50 SPS down to 10 MΩ at ≥2 kSPS).
3. The SYNC/PDWN trap. Holding it low for 20 DRDY cycles puts the device in power-down — oscillator and clock output included — and no serial communication is possible while it's low. This is the classic "my SPI hung" cause.
4. Wake-up delays. From power-down, a crystal needs ~30 ms to wake; with an external clock, wait 8192 CLKIN cycles before conversions begin. One-shot mode also needs up to 64 modulator clocks (≈33.3 µs at 7.68 MHz) of settle time before the first valid data.
5. Absolute maximums. AGND to DGND must stay within ±0.3 V; AVDD −0.3 to +6 V; DVDD −0.3 to +3.6 V; analog inputs −0.3 to AVDD + 0.3 V; digital inputs (DIN, SCLK, CS, RESET, SYNC/PDWN, XTAL1/CLKIN to DGND) −0.3 to +6 V; digital I/O (D0–D3 to DGND) −0.3 to DVDD + 0.3 V; input current 100 mA momentary / 10 mA continuous.
6. Spec conditions. Electrical characteristics assume −40 to +85 °C, AVDD = +5 V, DVDD = +1.8 V, f_CLKIN = 7.68 MHz, PGA = 1, V_REF = +2.5 V. Off those conditions, check the figures, not the headline numbers.

How to test it

1. Reset first. After power-up, reset via the RESET pin or the RESET command (which restores register defaults). If the part is stuck in Read Data Continuous mode, issue SDATAC first so it can accept commands — but note SDATAC only exits that mode; it does not reset registers or internal logic. Respect wake-up delays before expecting anything.
2. Verify the SPI link. Write a known pattern to a register and read it back. A corrupt round-trip means an SCLK/CS level or timing problem, not a logic bug. Timing to meet: SCLK high and low ≥ 200 ns each, DIN setup/hold 50 ns, and inter-command gaps (t11) of 4 τ_CLKIN for RREG/WREG/RDATA and 24 τ_CLKIN for RDATAC/SYNC; calibration commands require waiting on DRDY instead.
3. Verify conversions. Confirm DRDY pulses at the configured data rate and read with RDATA when DRDY goes low. Remember: single-cycle settling after a properly restarted conversion — but if you change the MUX on-the-fly during free-running continuous conversion without issuing SYNC (or otherwise restarting the filter), the next DRDY's data is a mix of old and new inputs and must be discarded.
4. Run calibrations — only after DRDY goes high at the start, and send no further commands until DRDY goes low:
   • SELFCAL: disconnects the inputs and updates OFC/FSC. Takes 417 µs at 30 kSPS/PGA=1 up to 827 ms at 2.5 SPS (self gain). With inputs shorted, the code should sit near zero afterward.
   • SYSGCAL: apply a full-scale input of at least 80% of full-scale; updates FSC. 417 µs @ 30 kSPS to 800.4 ms @ 2.5 SPS. With a precision reference applied, the code should reflect it.
5. Sweep the input with the buffer on to confirm linearity holds within the AGND-to-(AVDD − 2 V) window before trusting absolute accuracy near the top of range.
6. Sensor-detect check. Enable SDCS at a small current (0.5 µA for low sensor resistance) and classify short vs. open vs. good by the measured IR drop: a true short still shows I_SDC × 50 Ω residual (two internal 25 Ω MUX switches); an open produces a very large signal. Note: enabling SDCS forces the input buffer on regardless of BUFEN, and AINp must stay below 3 V or the clamp sinks current.

How to troubleshoot it

• SPI hung / unresponsive? First check SYNC/PDWN isn't held low. Then use the built-in recovery: if SCLK is held low for 32 DRDY periods, the serial interface resets itself and the next SCLK pulse starts a fresh cycle. When idle, hold SCLK low, not high.
• Garbled register reads? SCLK is Schmitt-triggered, but glitches can shift data. Fix signal integrity (short traces, no overshoot) before chasing firmware.
• Part in a bad state? Do a clean reset — RESET pin low, RESET command, or the special SCLK reset pattern — rather than repeatedly poking registers.
• Stuck DRDY / no new data? You're probably in power-down, or reading DRDY too soon after wake (the ~30 ms crystal / 8192 CLKIN-cycle wait is expected, not a fault).
• Codes compress near full scale? Buffer on and the input is riding above AVDD − 2.0 V. Bring it back into the window.
• Erratic readings on all channels? Check the ground split and supply limits before suspecting the ADC — an AGND/DGND violation is a common root cause.
• Dropping samples after MUX changes? If you issue SYNC (or restart the filter) after each MUX change, the part settles in one cycle and nothing needs discarding; if you switch channels mid-stream in continuous mode without restarting, discard the next sample. If data still looks stale, the problem is your DRDY handshake, not settling.

One last myth to retire: "more data rate is free." The digital filter is a fixed 5th-order sinc (decimation 64) plus a programmable average set by DRATE — fewer averages means less filtering. The notches land at the data rate and its multiples, so pick your rate deliberately: 2.5/5/10/15/30/60 SPS notch 60 Hz, 2.5/25/50 SPS notch 50 Hz, and 2.5/5/10 SPS reject both at once — which are also the highest-resolution rates. For a slow mains-powered measurement, you don't trade resolution for line rejection; you get both.

Part page: ADS1255